Hello all, I imported a verilog netlist for a layout previously designed in Encounter. When I try to open the schematic and hit check&save, I get these errors: Error: Net "v_CALCULATION_CNTR " shorted to net "N5512,N5511,N5510,N5509,N5508,N5507,N5506,SYNOPSY S_UNCONNECTED__0". Error: (DB-270004): Illegal bus reference - Can't tap " " from net "v_CALCULATION_CNTR ". Error: (DB-270004): Illegal bus reference - Can't tap " " from net "v_CALCULATION_CNTR ". Error: (DB-270004): Illegal bus reference - Can't tap " " from net "v_CALCULATION_CNTR ". Error: (DB-270004): Illegal bus reference - Can't tap " " from net "v_CALCULATION_CNTR ". Error: (DB-270004): Illegal bus reference - Can't tap " " from net "v_CALCULATION_CNTR ". Error: (DB-270004): Illegal bus reference - Can't tap " " from net "v_CALCULATION_CNTR ". Error: (DB-270004): Illegal bus reference - Can't tap " " from net "v_CALCULATION_CNTR ". INFO (SCH-1172): There were 8 errors and 0 warnings found in "NangateOpenCellLibrary key_expansion_KEY_SIZE0 schematic". Moreover, I can see lots of unconnected wires like the attached picture This verilog netlist was exported from SoC Encounter from a layout with no geometry or connectivity violations. Any suggestions ? EDIT: the unconnected wires are probably due to some floating output pins of std cells that are not used in the design and I don't see errors complaining about them.
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Forum Post: Cadence Virtuoso: Import a large verilog netlist to cadence schematic
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Forum Post: RE: Assura problems with feedthrough caps
Hi Andrew, Yes, i guess it would be difficult but thanks anyway. I progress a little bit. Just in case it can be useful to somebody: I am having around 10000 ambiguities but if I increase the threshold to 20000 assura provides a clean LVS. The clean LVS does not satisfy me completely and I am try to understand the nature of these ambiguities to avoid them when possible and understand why assura expands the feedthrough cells (they are MOS caps with D and S shorted to the same potential). Somebody can tell me when or in which conditions assura expands a cell? in my case schematic hierarchy and layout hierarchy are equal. Regards, Manuel
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Forum Post: RE: Donut Pad to Ground Connection
In the Symbol Editor, Edit>Properties, Pins On in Find, pick the Pin with a left-click, locate the Dyn_Thermal_Conn_Type entry in Edit Property and select it, use Assign, and set None for the Type for Cdn_Inner_Plane and Cdn_Inner_Signal, for example to prevent connection. (You can set other layers and options for the Thermal Connection Type)
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Forum Post: Arguments in geOpen()
Hi, its showing an error for geOpen() with some arguments as missing, even after i specifed the every argument. geOpen(w_Window, library, cell, "schematic" "schematic" "r"), where i specified my window as w_window = hiOpenWindow(), library is library am using, cell is cell View and r is mode. Thanks. w_window = hiOpenWindow() w_window = hiOpenWindow()
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Forum Post: RE: layout dynamic selection accessibility?
In IC617 and ICADV122/123 the out-of-context (i.e. unselectable) items are now shown black (rather than grey) like the rest, but are shown italicised to make it easier to read. The answer to your section question is "no". Andrew.
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Forum Post: RE: lxCheck but with useful return?
Dan, Try this: procedure(CCFlxCheck(cv) let(((port outstring())) ; might not want to capture the warnings - if not, miss out the (woport port) bit let(((woport port) (poport port)) lxCheck(cv) ) prog1( getOutstring(port) close(port) ) ) ) Then you can do: report=CCFlxCheck(cv) You'll get the text in a string - you could then use parseString(report "\n") to get a list of lines at the newline separators and so on. The above works by opening an output port which writes into a string, and then temporary redirects poport/woport to write to that port (this uses dynamic scoping so that when the stack unwinds the ports are correctly restored). No temporary files were harmed in the execution of this function ;-) Regards, Andrew.
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Forum Post: RE: Cadence Virtuoso: Import a large verilog netlist to cadence schematic
Thanks Andrew for your reply. I'll try a more recent IC version, but one more simple question.. in the design verilog netlist every std cell has "VDD"&"VSS" as power ports, while in the std cell Library, the std cells schematics has "VDD!"&"VSS!" as their ports (I understand what you told me before, but can this be a mismatch ?). If it will not result in mismatch, then I should specify "VDD"&"VSS" as global power nets in Verilog In window, correct ? Thank you!
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Forum Post: RE: Cadence Virtuoso: Import a large verilog netlist to cadence schematic
As I've said before, having power nets in the verilog won't help you since the symbols don't have power and ground nets. Similarly the verilog descriptions of the standard cells don't have power and ground nets. It's irrelevant what you specify as the global nets in the Verilog In form because those nets wouldn't be in the Verilog netlist (unless you've used the inherited connections trick I mentioned before, or you've got explicit pins everywhere, which probably doesn't make sense as part of a flow). I suspect all you need to do is ensure that the top level pins (on your P&R block) are called VDD! and VSS! or you have made those equivalent to VDD and VSS respectively (I expect Calibre LVS allows you to do this). I doubt it's essential for the pins to match on the netlist and layout at each and every level of hierarchy, or there's probably a way of mapping them somehow in Calibre. However, not a tool I have really used (as I work for Cadence not Mentor). Andrew.
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Forum Post: Storing config of a cell in a file/cellview
Hi, Is it somehow possible to store design variables of a cell in a config-like cellview or file? Here is what I mean: Suppose I design a simple opamp for I which create a triangle symbol view and use it in many other places. Now when I design the amplifier I have all the widths, lengths, bias currents in my ADE L view as Design Variables. I can sweep them until they match and then I fix them. Now, 2 weeks later I need to change the amplifier. I need to replace all the static values by design variables, design the amplifier and re-replace the values again with their static values. This is extremely error prone (and I always make mistakes), particularly since so many values are interrelates (e.g. the widths in a differential configuration are the same and the biasing branches are just some multiple). What I envison is some sort of pPar which takes the actual values from a config file or config cell view. Then it's also way easier to keep an overview on the design and archive specs. What I do not want: Store the values in an scs file and use "Simulation files". It just does not work because ADE L always imports the design variables into the window and then simulation fails if if they are not set (and if they are set, they overwrite the values from the scs file). Supposedly copyDesignVarsFromCellview should fix this (see ) but this is just ignored. (Even if, I would not consider it a clean solution copyDesignVarsFromCellview copyDesignVarsFromCellview copyDesignVarsFromCellview)
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Forum Post: multi-technology simulation netlisting through command line.
Hi, All, I am doing top level mixed-signal multi-technology simulation (MTS). To generate a mutli-technology analog netlist, I need to start ADE XL GUI, config it into MTS mode, and generate netlist through GUI. Wondering whether there is a way to generate the MTS netlist through command line? Like: bsub -I virtuoso -nograph +(arguments to invoke ADE XL and generate the netlist) Thanks a lot for helping!
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Forum Post: RE: lxCheck but with useful return?
Thanks! Works like a champ. -Dan
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Forum Post: BER test setup in cadence
hi my question is regarding BER testing. I want to check the BER for OOK modulator/demodulator. I tried to find (in forum discussions) the setup/instances that may help to make setup for BER testing. Kindly guide is there any instance/setup avaialbe? Thanks
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Forum Post: Trying to generate abstract using absAbstract() command
Hi All, I executed below steps in CIW. I am using Virtuoso 6.1.6 version. My main aim is to generate lef from layout without any GUI windows. absSkillMode() absSetLibrary("venu") absSelCell("INV") absPins() But I am not getting any output view from above commands in my library . Could you please help me ? Thank you, Venu
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Forum Post: when is .cdsinit.local loaded?
I have a questions on .cdsinit.local file I did some customization (bindkeys etc.) in .cdsinit.local file and I put the file in my cadence working directory. When I start cadence, when is .cdsinit.local loaded? What I found is that some of the customization gets overwritten by scripts loaded later from the project/company environment. As a results, I have to load again my bindkeys after cadence fully starts. Is there a way to put .cdsinit.local at the end of the list of files loaded when cadence starts, so that it won't get overwritten? Or is there a way to use the pop up window (like the what's new window) to trigger the loading of some skill code? Thanks!
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Forum Post: Capture CIS Database setup using Orcale 11g
Hi, Can we setup Capture.ini file and DBC configuration file to link to database systems like Oracle 11g. Regards, Vinay
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Forum Post: RE: Capture CIS Database setup using Orcale 11g
You will need to have an ODBC driver for the Oracle database, 32-bit for 16.x and 64-bit for 17.x, installed. Then configure a datasource through Control Panel for the database using the ODBC drivers and then use CIS Configuration to build the DBC file to map the database fields from the datasource to Capture CIS fields.
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Forum Post: Calibre LVS errors for a design generated in Encounter
Hello all, I made a design in SoC Encounter using NangateOpenCellLibrary 45nm. The layout had zero geometry and connectivity violations. I then needed to go to Calibre for LVS and PEX in order to do post-layout simulations, so I did the following in Encounter: 1) Design > Save > GDS/OASIS, then I provided the map file and merged library gds file that came with PDK "NangateOpenCellLibrary.gds" and didn't select "Uniquify cell names"....then finally hit Ok. 2)Design > Save > Netlist, and I selected the two options in the window and hit Ok. Then for Calibre part: 1) I run "v2lvs" command to generate spice netlist for LVS 2) I then run LVS using Calibre -gui In LVS transcript window, I get tons of these two warnings: Open circuit - Same name on different nets: Top level port name "KEXP0/n2089" at location (3.515,165.69) on net 2 not valid for netlisting; net id used instead. (I think the above warning is the reason of the errors) and in the LVS report I get these: Error: Different numbers of ports (see below). Error: Different numbers of nets (see below). Error: Different numbers of instances (see below). Error: Connectivity errors. Error: Property errors. Warning: Unbalanced smashed mosfets were matched. Warning: Ambiguity points were found and resolved arbitrarily. Warning: LVS property resolution maximum exceeded. NUMBERS OF OBJECTS AFTER TRANSFORMATION --------------------------------------- Layout Source Component Type ------ ------ ------------- Ports: 12065 35 * Nets: 29877 29720 * Instances: 1265 1261 * MN (4 pins) 790 790 MP (4 pins) 5781 0 * _invb (6 pins) 10551 16326 * _invv (4 pins) (If you added instance "_invb" and "_invv" in both layout and source, they have the same total) I don't have experience to debug these errors, so can anyone tell me how to debug them ?
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Forum Post: searching just one forum
It looks like the search on the upper toolbar searches everything . Is there a local search on this new website to just search one forum ?
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Forum Post: RE: Calibre LVS errors for a design generated in Encounter
In Encounter, when I run this command "saveNetlist design.v -phys" I get this warning: No Power/Ground connections in top module (design). Pwr name (VDD). Gnd name (VSS). 1 Pwr names and 1 Gnd names. Creating all pg connections for top cell (design). Can this be related to the LVS problem ?
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Forum Post: RE: multi-technology simulation netlisting through command line.
Not as far as I know. Normally the MTS netlists are only produced when you actually simulate. To have some means to batch create the netlists would probably require an enhancement request. Regards, Andrew.
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