You would have to use the abstract executable, not the CIW. Andrew.
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Forum Post: RE: Trying to generate abstract using absAbstract() command
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Forum Post: RE: multi-technology simulation netlisting through command line.
Got it. Thanks Andrew. Hopefully this function can be built in the future updates.
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Forum Post: RE: multi-technology simulation netlisting through command line.
[quote user="Muddler Wang"]Hopefully this function can be built in the future updates[/quote] It's unlikely it would be unless you actually request it (this is not the place to make enhancement requests; you need to do that via support.cadence.com )
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Forum Post: RE: multi-technology simulation netlisting through command line.
I see, I will make a request there. Thanks a lot Andrew!
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Forum Post: linux spb17.0 startup problem
hi, guys: I want to launch the allegro inside the installed spb 17.0 as following: $:cd /opt/cadence/SPB17/tools.lnx86/bin/allegro_cshrc $:csh $:source allegro_cshrc $:allegro & the terminal shows problem like this : /opt/cadence/SPB17/tools.lnx86/bin/apd.exe: symbol lookup error: /usr/lib/x86_64-linux-gnu/libXext.so.6: undefined symbol: _XGetRequest and I have checked that this path: /usr/lib/x86_64-linux-gnu/ does have libXext.so.6 so how should i do to make it right? thanks in advance!
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Forum Post: RE: Trying to generate abstract using absAbstract() command
Thanks Andrew. Yes it is working with abstract executable gui window. I am looking for command to execute pins,extract, abstract from CIW without abstract gui window. Is there any way of executing abstract from CIW window itself?
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Forum Post: RE: layer map file for GDS transfer to virtuoso
you need the stream-in map, which should have come with the PDK. It's not the same format as the Encounter streamOut map. since this question is virtuoso-centric, maybe post to the Custom IC forum. There might be someone there who can tell you exactly what file to look for or where to find it.
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Forum Post: RE: Calibre LVS errors for a design generated in Encounter
"same name on different nets" means that you have an open. the net in question has two pieces that do not connect together. Is this intended? If so, you can either ignore the warning or use a virtual connect. it's hard to debug the other things without having the design.
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Forum Post: RE: Calibre LVS errors for a design generated in Encounter
Yes, this can very likely be causing your LVS issues. Did you use the globalNetConnect command to say that your std cell pwr/gnd pins are connected to VDD/VSS? If not, these connections will not be written out in the physical verilog.
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Forum Post: RE: IO Ring lef files TSMC65
This question might be more targeted for the Custom IC forum, but if you have LEF, shouldn't you do a LEF-in? StreamIn is for GDS. (Been many years since I used Virtuoso though, so I apologize if this doesn't make sense.)
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Forum Post: RE: generate power grid library
You can, but I would ask the library vendor for the extracted spice for the std cells. There are probably lots of ways to create the list of std cells. I grep the LEF files for MACRO and then do some file manipulation to get it.
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Forum Post: RE: Calibre LVS errors for a design generated in Encounter
No it was not intended. But, how on earth I have open circuit and the layout has no geometry and connectivity violations in Encounter ? Moreover, do I need to re-run the whole flow again or there is an easier way to fix it ? If there is an easier way than re-running the flow, please tell some hints on how to debug these issues as I don't have much experience. Thanks
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Forum Post: RE: Calibre LVS errors for a design generated in Encounter
yes, I used globalNetConnect in GUI. Connection list: VDD:PIN:*.VDD:Module() VSS:PIN:*.VSS:Module() Should I have tied VDD to high and VSS to low ?
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Forum Post: SKILL pPar error during CDF parameter handling
Hi all, I'm trying to pass parameters from the top level schematic to a lower level schematic. The schematic and CDF parameters are generated without problems, but when I try to modify the value of existing schematic components (in this case only inductor is present) and insert pPar("__CDFparName__"), I get an error which says that pPar is an undefined function. Both schematic and symbol are created using dbOpenCellViewByType. The procedure is presented below: procedure( pcellTestProc(LIB_NAME CELL_NAME VIEW_NAME ) let((params cellId cdfId cvSchem) cvSchem = dbOpenCellViewByType(LIB_NAME CELL_NAME "schematic" "schematic" "w") dbReopen(cvSchem "a") unless( cellId = ddGetObj( LIB_NAME CELL_NAME ) error( "Could not get cell %s." CELL_NAME ) ) when( cdfId = cdfGetBaseCellCDF( cellId ) cdfDeleteCDF( cdfId ) ) ; insert inductor "ind" from library "analogLib" params = insertInstance(LIB_NAME CELL_NAME VIEW_NAME "analogLib" "ind" "symbol" "Lpkg" 1 0:0 1:0 "R90") cdfId = cdfCreateBaseCellCDF( cellId ) ; Parameters for the cdfCreateParam( cdfId ?name "extParamL" ?prompt "inductance" ?defValue "" ?type "string" ?display "" ?parseAsCEL "yes" ) cdfSaveCDF( cdfId ) ; change value params~>l = pPar("model") ;<------------------------ HERE'S WHERE I GET AN ERROR: *Error* eval: undefined function - pPar dbSave(cvSchem) dbClose(cvSchem) );let );procedure How are pPar values passed on to the exiting component parameters via SKILL, where did I go wrong with my approach? Thanks, Aleksandr
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Forum Post: RE: SKILL pPar error during CDF parameter handling
Hi Aleksandr, The property type is a string, so the pPar call needs to be formatted as a string (you don't want to try and call a SKILL function named pPar() now, it is to be evaluated later, e.g. during netlisting): params~>l = "pPar(\"model\")" Hopefully this will resolve the issue? Best regards, Lawrence.
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Forum Post: RE: SKILL pPar error during CDF parameter handling
Hi Lawrence, Thanks for the lightning response. Yes, that fixed the issue. Thanks! Aleksandr
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Forum Post: RE: Calibre LVS errors for a design generated in Encounter
I don't use the gui for globalNetConnect, I use the commands. Something like: globalNetConnect VSS -type pgpin -pin VSS -all -override -verbose globalNetConnect VSS -type tielo -all -override -verbose globalNetConnect VDD -type pgpin -pin VDD -all -override -verbose globalNetConnect VDD -type tiehi -all -override -verbose Is the net that LVS says is open, a pwr/gnd net or a signal net? Do you have a pwr/gnd grid that actually connects all the cells together? Also, I haven't used Calibre for years, so I may not be leading you down the right path to solve this. Or it could be some other issue that makes it look like that net is open - really hard to tell without being able to poke around in the design.
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Forum Post: DRC error on regulator output
DE CIS is giving a DRC error on my 5V regulator output because it is connected to a power NET called VCC_BAR. "ERROR(ORCAP-1628): Possible pin type conflict U13,OUT Output Connected to Power" Obviously the error is caused by the fact that the LM7805 OUT pin is identified as a Output pin, which is a fact, And also because the DRC rules in my schematic are set accordingly. Power to Output =>Error The question is: How do I handle this in the proper way? Changing the part pin to passive eliminate the error but it does not represent the reality. Power Regulators are utilized all the time for PC-board power and the output must be connected to a power NET. How is this situation handled with respect of the rules and regulations of the PC-board industry ? Cheers
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Forum Post: Problem saving intrinsic parameters using save statement save NM0:all
Hello all, I know this has been addressed several times before as I've searched the forum before actually asking this question but I have tried the solutions but nothing seems to work. I'm trying to characterize an NMOS using the gm/Id technique which requires me to save the intrinsic parameters such as gm,gds,fT while the Vgs is being swept for a range of values. For this I have used the save NM0:all statement, saved it in a .scs file and have included it in the netlist as shown below. Spectre then gave a warning saying the following: "WARNING: subcktInst:all is not supported. WARNING (SPECTRE-8287): Ignoring invalid item `NM0:all' in save statement." I then followed Andrew Beckett's advice on another post about saving Subcircuit stuff as per the following link [1] , and changed the save statement to save NM0.nm_hp:all, in which Spectre gives the following warning:- "WARNING (SPECTRE-8282): `NM0.nm_hp' is not a device or subcircuit instance name. WARNING (SPECTRE-8287): Ignoring invalid item `NM0.nm_hp:all' in save statement. " I can confirm that the transistor I am using is a subcircuit with the name nm_hp as the model file has the following lines, subckt nm_hp ( d g s b ) parameters My question is, what am I doing wrong here? I have included all the appropriate model files and netlists and nothing seems to work. I can't for the life of me figure out what's wrong. I have attached the netlist below. Whelp? Netlist:- NM0 (vdd! net2 0 vdd!) nm_hp w=(4u) l=(130n) as=1.36p ad=1.36p ps=8.68u \ pd=8.68u m=1 sa=340n sb=340n sd=0 nf=1 V1 (vdd! 0) vsource dc=600.0m type=dc V0 (net2 0) vsource dc=600.0m type=dc simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ checklimitdest=psf dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status dcOpInfo info what=oppoint where=rawfile dc dc dev=V0 param=dc start=0.2 stop=1.2 step=0.05 oppoint=rawfile \ maxiters=150 maxsteps=10000 annotate=status modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile save NM0.nm_hp:all saveOptions options save=allpub [1] community.cadence.com/.../26938 ;ReplyToContentTypeID=0
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Forum Post: RE: Storing config of a cell in a file/cellview
Hi itos When tuning device parameters, it is actually no longer necessary to go through the traditional method of replacing the property fields with ADE variables. In both Explorer, Assembler and also ADE-XL, we can use the "Variables and Parameters" assistant as follows: a. Select the target device in schematic b. Parametrized the required device parameter as follows in the "Variables and Parameters" assistant c. Replacing the value in the assistant does not affect the schematic. The new value will be automatically used in Spectre netlist d. Perform simulation and tune parameter until the specs have been meet In this snapshot, I have parametrize "w" for device M1. We can see that the design (schematic) value is 10u but I have changed it to 11u in the assistant. 11u and not the original 10u will be used in the netlist. If you have access to ADE-XL, I think this might be what you need. Best regards Quek
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