In the AWR Design Environment platform, V16 software , you can now associate schematics with a process library. When an older project is loaded into the V16 software, if the project uses a single process library, all schematics are automatically configured to use that library. If the project uses more than one library, the library settings for each schematic are based upon which LPF the schematic uses. When reading an old project file that does not have PDK settings for schematics, if the AWR Design Environment software cannot determine which PDK to associate with a schematic, the following dialog box displays to prompt you to choose the PDK. This has been added to the V16 and higher versions. Team SimTech Cadence Design Systems
↧
Forum Post: New in V16 – Associating Schematics with Process Library in AWR tool
↧
Forum Post: RE: Generate layout from symbols with design variables
Thanks Andrew, my problem was solved. I found the following request's solution which worked for me. For sharing. https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000002JngkEAC&pageName=ArticleContent&caseSessionKey=0053w000008kZa9AAE__20220525163022917 In summary, in the .cdsinit and .cdsenv, adding the following statements: In .cdsenv, the syntax is: layoutXL lxEvalCDFCallbacks 'boolean t In .cdsinit or CIW, the syntax is: envSetVal("layoutXL" "lxEvalCDFCallbacks" 'boolean t )
↧
↧
Forum Post: How can I assign ground shape 20 mil away from the outline using PCB editor 17.4?
My Dynamic shape is pouring over the route keepin?? The Blue is the route keepin. Dk Green is the design outline. And yet the dynamic copper (green) has poured over both the routein AND the design outline?? What has gone wrong here?
↧
Forum Post: RE: How to create layout labels automatically
Thank you Andrew for your try and efforts, I am shy to tell you that I don't know how to contact the customer support, because when I click the link of "customer support" it take me to the support home page and I can not find the contact link there Than you once again Regards
↧
Forum Post: RE: How to create layout labels automatically
You log into the support site and then use this: Cases->Submit Case - then then fill in the form with the details. Regards, Andrew
↧
↧
Forum Post: Packaging made easy - Advanced Annotation
Capture packages components on the fly. When Auto Reference is enabled, any new part in the design gets a unique reference designator automatically. You don’t really need to manually annotate the design. Still, if you want some custom refdes ranges, Capture has you covered. Use the Advanced Annotation feature to assign references on selective pages, blocks, and even based on property values. You can open the Advanced Annotation UI from the Annotate dialog. Regards Team DesignTech Cadence Design Systems
↧
Forum Post: RE: How to remove FPC connector symbol from BOTTOM-Layer?
I have difficulties understanding your comment. If you would place punctuation marks where appropriate, it would ease that task for me. Any further answers are welcome.
↧
Forum Post: Top-Level RC Extraction with black box option
Hello I have read the document Circuit Physical Verification and Parasitic Extraction, Rapid Adoption Kit (RAK), Product Version: PVS19.12, Quantus20.10 June 2020 In particular, I am interested in running the LVS for the top hierarchal level which includes already verified layout blocks. Hence the top abstract contains those cells plus the interconnection between them and to the pads. According to this manual, it is recommended to run LVS by treating the lower layout cells as a back box. I couldn't understand from the manual the idea of black box because from what I read it looks to me that the tool treat those boxes as a box with the extended pins for next verification of LVS, and then the QRC extractor will only exctract the parasatic of the top level connections. Ofcourse I am not sure about my conclusion, but if my understanding is right it means the post-layout simulation will only reflect the fact due to the top-level parasitic. It would be helpful if you explain me the advantage of black box and the difference in case if I used the regular LVS without black box. Thank you in advance Best Regards
↧
Forum Post: RE: Assembler: possible to re-evaluate only results yielding "eval err" right after simulation?
Hi Jorge, I can think of a SKILL way of forcing problematic expressions to appear changed so that incremental re-evaluation handles this (it's not ideal though because the approach I had in mind would mean that a given output name would re-evaluate all even if it only failed in some corners). Probably the best thing to do here is to solve your underlying problem, which is (most likely) due to using LSCS in more recent versions. For that, the expressions are evaluated in a separate, more lightweight process, and any custom functions need to be loaded from a file call .vdsinit rather than .cdsinit . The idea is that this doesn't attempt to load the full customisation for Virtuoso but keeps it to the bare minimum. Try loading your function from a .vdsinit and see if that solves the real problem of it not evaluating during the run. I'm pretty sure this is it, because you refer to the exprOutputs.log which only gets created with the newer LSCS flow. Regards, Andrew
↧
↧
Forum Post: RE: How to obtain Discrete-Time (DT) response from a switched-cap (SC) circuit (integrator)?
Dear Frank ( & Andrew), Yes, ok, that the PAC measures the amplitude and just plots it at the already known input frequency. => I am sorry, this was a stupid one, I don’t know, how it could not have been clear to me without your last add-on. But is the rest of my short summary so far ok at least, “how I can imagine the PAC sampled is working”? -------------- However, an important stuff is the following: For case B) (= the SC-filter), you proposed to do zero-stuffing ( = only take every 10th sample and just REPLACE the others by “0”). This then was matching to the PAC sampled, option “ ris. edge ” perfectly (!!), because I also did herewith “ideal Dirac sampling” (but with additional unfiltered decimation by factor 10), see e.g. in below picture the black, red, orange columns “B”, “L”, and “V” for easier understanding. Subsequently, for comparison, I also did a zero-stuffing with up-sampling ( = higher fs). See the black, blue, green, and pink values. Herewith, I “suddenly” now match to the “PAC sampled, option “ time averaged ”. My “DT response” (see red line, left graph) is gone (see red line, right graph), even BEFORE it is flavored with the comb-filtering (right pic, cyan). And, moreover, if I do the “replacing zero-stuffing procedure” but with factor 5 or 20, I get again other results than the PAC (not shown, e.g. 2 "peaks" at only 2kHz and 4kHz instead). It just was “by chance” the factor 10 correct, but I mean, I cannot adapt my analysis each time to the DUT! The analysis process has to be stupidly every time the same, regardless which circuit I am analyzing with it! So: ==> What can I do, in order to match with the same procedure of any DUT to the same PAC option every time? Maybe my idea now is to sample even again e.g. a factor 10 higher and then do not look to the results from (fs/2)/10 until (fs/2) ?? (A sim. for that is running already, but it is running since some days now for just this little circuits.) I would like to can say: With doing “brute-force zero-stuffing” = a reasonable factor, say 10, for doing ideal Dirac sampling and thus replacing the rest with zeros, I always resemble from DC until “(fs/2)/10” the PAC sampled, option “(ris./fal.) edge”. And when I subsequently comb-filter it, I always resemble the PAC sampled, option “time avg.” So something like this I have in mind. (click to enlarge) Left: Orig & Zero-stuffed with same fs (“replace by 0”) Right: Orig & Zero-stfd. w. higher fs (“up-sample”), shown to orig. fs/2 -------------- You write: “ normal PAC and sampled PAC are different analysis types ”. We previously said: “normal PAC = “PAC sampled, time avg.” (e.g. Andrew correct?). To be now more precise, we can re-write it into: “ ‘PAC sampled, time avg.’ and ‘PAC sampled, (ris. or fal.) edge’ are different analysis types”. You said, I can imagine the later to do “(min-max)/2” (see above for details) which perfectly worked. => How can I imagine the “PAC sampled, time avg. ” to be working then? -------------- Obviously, this thread has caught the interest of a lot of other people in the meantime, and so I say to you “Thanks so much for your help again”, it seems to be not only good for me... bernd2700
↧
Forum Post: RE: How to create layout labels automatically
Thank you Andrew for your reply and help Best Regards
↧
Forum Post: RE: How to obtain Discrete-Time (DT) response from a switched-cap (SC) circuit (integrator)?
[quote userid="538772" url="~/cadence_technology_forums/f/custom-ic-design/51410/how-to-obtain-discrete-time-dt-response-from-a-switched-cap-sc-circuit-integrator/1383460#1383460"]For case B) (= the SC-filter), you proposed to do zero-stuffing ( = only take every 10th sample and just REPLACE the others by “0”).[/quote] The factor 10 was because in your transient simulation, you were sampling at a 10x higher frequency than the frequency at which your sample-and-hold was running, so that you were getting 10 identical samples in a row each time. [quote userid="538772" url="~/cadence_technology_forums/f/custom-ic-design/51410/how-to-obtain-discrete-time-dt-response-from-a-switched-cap-sc-circuit-integrator/1383460#1383460"]What can I do, in order to match with the same procedure of any DUT to the same PAC option every time?[/quote] For the sampled PAC analysis, sample the result of the transient simulation at the same frequency as the PSS fundamental frequency (and at the same position in the PSS period as is specified by the setup for the sampled PAC analysis). [quote userid="538772" url="~/cadence_technology_forums/f/custom-ic-design/51410/how-to-obtain-discrete-time-dt-response-from-a-switched-cap-sc-circuit-integrator/1383460#1383460"]How can I imagine the “PAC sampled, time avg. ” to be working then?[/quote][quote userid="4061" url="~/cadence_technology_forums/f/custom-ic-design/51410/how-to-obtain-discrete-time-dt-response-from-a-switched-cap-sc-circuit-integrator/1383289#1383289"]This is just the nomal PAC analysis without any sampling, so you simply need to run an FFT on the output signal in order to get the result in the frequency domain.[/quote] What is probably confusing you is that fact that this result is also available in the Direct Plot Form after a sampled PAC analysis. When you sample the output of the transient simulation at higher and higher frequencies, your result is simply getting closer and closer to a Fourier transform of the complete output signal (which in this case is the piecewise constant output of the sample-and-hold). [quote userid="4061" url="~/cadence_technology_forums/f/custom-ic-design/51410/how-to-obtain-discrete-time-dt-response-from-a-switched-cap-sc-circuit-integrator/1383194#1383194"]By the way, the normal PAC analysis with maxsideband=0 like in my example also only looks at the output signal at the input frequency. For a piecewise constant signal, there will be additional frequency components in the spectrum, possibly with much larger amplitudes.[/quote]
↧
Forum Post: RE: Issue with awvPlotWaveform
Andrew, Sorry for the delay in response. Was really busy at work. The issue is not showing up any more. I dont think I changed anything(something could have happened inadvertently). The version we are using is "waves" is a list of waveforms. Since I dont know how to reproduce this issue, I cant share anything else that might be useful here.
↧
↧
Forum Post: Regular Expressions for ADEXL output filter
Is there any way to use regular expressions for the output filter on ADEXL? Thanks!
↧
Forum Post: RE: How can I assign ground shape 20 mil away from the outline using PCB editor 17.4?
Try Setup - User Preferences - Shapes - General - and enable shape_rki_autoclip then disable and renable then dynamic shape and see if that helps.
↧
Forum Post: RE: Orcad library files with file names with spaces are not supported in Allegro system capture
As per my understanding, design and library paths should not contain spaces
↧
Forum Post: Allegro - Tip of the Week: Want to delete a via that is part of a via stack?
Want to delete a via that is part of a via stack instead of deleting the entire via stack? Use Edit → Delete . Make sure that vias are selected in your Find panel. Left-click on the stacked via to select it, and then use the RMB (Right Mouse Button) → “Split Stack …" command. From the popup list, select the layer pair that needs to be deleted. Team PCBTech Cadence Design Systems
↧
↧
Forum Post: RE: Regular Expressions for ADEXL output filter
I assume you mean ADE Explorer/Assembler, rather than ADE XL since that doesn't have filters. Anyway, you can use Right Mouse over the filter field to control what type of match it is: There is not any support for regular expressions, but there is at least one request (CCR 1598792) asking for this (I found another similar request too which I've asked to be duplicated). You might want to contact customer support and request a duplicate be filed on your behalf. Andrew
↧
Forum Post: MMMC cdB library in Voltus or Tempus 21.10
Hi, I am using Innovus/Voltus/Tempus 21.10 but experiences a fatal error when loading the design finished by Innovus in Voltus or Tempus: (read_db -oa_lib_cell_view ; actually the first command in the init script ) **ERROR: (IMPESI-3490): cdB based analysis is not supported with CMMMC configuration. This may result in inaccurate analysis. Configure and run analysis in SMSC if using cdBs. The tool self-closes. The MMMC av definition includes library sets with -timing links to ecsm libraries as well as -si links to cdb libraries for signal integrity. The implementation flow with innovus runs succesfully but signoff tools complain about the cdb libraries. When I run implementation without cdb, it is loaded without errors in voltus/tempus. Same issue with flowkit/flowtool when si_files are defined . I'm using oa libraries throughout the entire flow. How should I load the oa library in voltus correctly and switch to SMSC? Or is the cdb based analysis deprecated? Similar report here: https://community.cadence.com/cadence_technology_forums/f/digital-implementation/49165/impesi-3490-error-in-tempus Thanks a lot!
↧
Forum Post: How to use ocnSetXLMode() command to set mode to XL.
Hello, I try to use python script to load ocean script automatically in virtuoso. Then I got an error: "Mode not set as XL. Use ocnSetXLMode() command to set mode to XL." I met this error at the first time. So what should I do? Change the ocean script? If anyone know this, please tell me. Thank you so much! Regards, Lingtao Jiang
↧