You seem very confused by relatively simple things - I suspect you're assigning more meaning to files than maybe they deserve. Let me explain a little about what these "spectre.dc", "spectre.ic" and "spectre.fc" files are. First of all, the naming of the files doesn't imply any meaning - it's just a matter of what ADE calls various files by default. If I turn on a DC operating point analysis, and a short transient and leave everything else as default in ADE, it netlists as: dcOp dc write=" spectre.dc " maxiters=150 maxsteps=10000 annotate=status dcOpInfo info what=oppoint where=rawfile tran tran stop=100n write=" spectre.ic " writefinal=" spectre.fc " \ annotate=status maxiters=5 The write parameter of an analysis (e.g. dc or tran) writes the DC solution from the beginning of the analysis. For a dc operating point, this is the value computed with all capacitors open, all inductors shorted, and all sources at their "dc" value (this means that if the dc value is set it uses that, otherwise it uses the time-zero value of the source). For a transient analysis, again all caps open and all inductors shorted, but it always uses the time-zero value of all the sources (so that the initial transient solution matches the value at the very first time point of the transient). So the spectre.dc and spectre.ic contents can be different. The writefinal parameter (available on dc and tran and a few others) is the solution at the end of the analysis. For a dc analysis this is useful if you did a dc sweep, and transient it's the solution at the end of the time simulation. All these files contain node voltages and some currents - they represent a "node set". The tran analysis has options on the Algorithm tab for readic and readns. (dc has equivalent options called readforce and readns). These allow you to read one of these types of files to give a starting condition. The readns will use the contents of the file as a starting point for the DC solution - it essentially drives each node by a 1 ohm resistor (by default) with the voltage at each node, and tries to reach convergence - then removes the sources and continues to reach convergence - so it's a hint to pull the solution in the right way and make it easier to converge by giving a decent (hopefully) starting point. With readic the difference is that it doesn't try to remove the forcing sources after converging - that is then the converged solution (they are then removed for the transient though). If you do skipdc=yes, it will just use the readic solution as-is and won't try to converge further - which may be a problem if the readic file doesn't match the circuit. It is not required to read these files - they are just a convergence aid. I suggest you read Ken Kundert's book - A Designer's Guide to SPICE and Spectre for more details on how to aid convergence. I doubt very much that using the initial transient solution from a much smaller circuit will help with the nodeset of the bigger circuit since three quarters of the circuit has no convergence aid, unless the convergence problem is in some common part of the circuit unrelated to the repeated part. I already explained how to add the +diagnose option to add more convergence diagnostics. If this isn't enough - you should contact customer support . Regards, Andrew.
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Forum Post: RE: How to reduce time needed before transient simulation to be started in case of large circuit
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Forum Post: RE: Virtuoso Analog Distributed Processing options default
Aldo, envSetVal("asimenv.distributed" "deleteJob" 'boolean t) envSetVal("asimenv.distributed" "removeJobData" 'boolean t) envSetVal("asimenv.distributed" "queueName" 'string "my queue") envSetVal("asimenv.distributed" "lsfResourceString" 'string "resource string") envSetVal("asimenv.distributed" "selectLsfResourceString" 'boolean t) envSetVal("asimenv.distributed" "drmsCommand" 'string "bsub -q myqueue") ; setting this will force it to use command mode Yes, these are documented. Search for lsfResourceString in cdnshelp and you'll find the relevant part of the manual. Andrew.
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Forum Post: RE: Converting a existing library to PCELL library
Ramakrishnan, I'm guessing that the symbols wouldn't need to be parameterised, and it's unclear to me whether the schematics do too. If so, a similar template-based approach might be the easiest if you need to switch a device depending on a parameter. Andrew.
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Forum Post: RE: Stop view
Probably a bit of a late reply, but the principles of switch view lists and stop lists are quite simple. The idea is that when the hierarchy is being traversed by the netlister, when it comes to an instance it will look along the view list in order and see if one of those views exists. Once a view is found it switches into that view. If the view that is switched into is in the stop list, no further hierarchical expansion is performed and netlisting is done using the simulation information in the CDF for that component (with a slight complication I'll mention in a moment). If it's not a stopping view, that view is then traversed and netlisted as a subckt (or similar depending on the netlister). The complication is that there's something called view-specific CDF which is where things like the veriloga analyser add some additional information in the CDF about a specific view. This is to allow (for example) multiple veriloga views with different terminal orders or different parameters. Anyway, if you add a spectre view then usually that is before veriloga in the switch view list, and hence it will stop expanding the hierarchy and netlist the component using the simulation information in the CDF. It will however not add the ahdl_include in the netlist because it is unaware of the veriloga view being used. Hopefully that helps! Andrew.
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Forum Post: RE: Thermal Noise of Resistor
Without seeing the architecture of your circuit, it's hard to be sure, but the mistake most people make is that the noise contributions you are seeing are output-referred noise rather than source-referred (i.e. the noise at the device itself). It is possible since SPECTRE161 (and later IC617 versions) to turn on "noise separation" on the noise form which allows you to see the noise at the device separately from the gain from the noise source to the output and the total noise. In my experience the noise analysis doesn't do the wrong thing - it's almost certainly correct circuit behaviour you're seeing or you're misinterpreting what the results mean. I'm happy to be proved wrong though! Regards, Andrew.
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Forum Post: RE: Auto Highlight in scroll Region
You can only highlight fields (using hiHighlightField) for type-in fields. You'd pass it the scrollRegion, then the fieldName and (say) hicHighlight as the third arg. You can use hiSetCurrentField which would scroll to the right field, but it doesn't highlight the row (for a checkbox). Andrew.
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Forum Post: RE: How to read a text file in a VerilogA code
Which simulator are you using and which version? I just took your code and added a little extra to make it complete: `include "disciplines.vams" module forum35 (a); output a; electrical a; real A,B,C,D; integer fid,retval; analog initial begin fid=$fopen("forumresults.csv","r"); retval=4; while(retval == 4) begin retval = $fscanf(fid, "%e,%e,%e,%e", A, B, C, D); $display("%e,%e,%e,%e", A, B, C, D); end end endmodule It then worked fine (I changed the filename). I see: Reading file: /export/home/username/tools/spectre/forumresults.csv 3.290000e-06,1.280000e+06,4.957780e-01,1.940000e-07 3.320000e-06,1.290000e+06,4.948000e-01,1.920000e-07 3.420000e-06,1.330000e+06,4.956510e-01,1.870000e-07 3.420000e-06,1.330000e+06,4.956510e-01,1.870000e-07 The last line would be a duplicate because retval would probably have been -1 for end of file (I didn't check). This is using Spectre16.1 - but would be a bit surprised if this is particularly fussy about the version... Andrew.
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Forum Post: RE: HB analysis results with different SELECT options
I can only imagine that your port impedance isn't 50 ohms or at least doesn't match the value on the direct plot form. The terminal versions use the current through the pin and the voltage on the pin to work out the power; the "port" option retrieves the simulated port impedance and uses that with the voltage to compute the power. The "net" options use the specified port impedance (on the form) to compute the power from the voltage measured.
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Forum Post: RE: Schematic export
Doing this kind of migration via EDIF or (even worse) Verilog is a good way of losing information and complicating matters. I have posted some code to help with doing this kind of migration - such as in this post . However, it may be difficult if the symbols don't match. Probably best to talk to customer support about this so we can help assess your precise needs. Regards, Andrew.
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Forum Post: RE: Matlab Simulink Coupler issue
Oliver, Please contact customer support - there is a newer version of the tutorial (not updated in the release yet) which can be supplied. Regards, Andrew.
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Forum Post: RE: Running multiple using ADE L, ADE XL, (not at the same time)
Menghan, In general, the latest hotfix should be the most bug-free unless there's a known problem we've introduced. So I'd say IC617 ISR13 (at this time). As for the multiple session problem - if you're having issues with that, you should contact customer support via your normal channel to report the scenarios where they occur. Andrew.
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Forum Post: RE: How to traverse PSF simulation results programmatically with SKILL/OCEAN
Hans, Does selectResult('dcOpInfo) report(?type "bsim4" ?param "vth") do the job for you? The results browser is not written in SKILL so that won't help you. The above will give you the vth operating parameter for all devices of type bsim4. Regards, Andrew.
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Forum Post: RE: Export simulation results from Virtuoso 6.1.6
I have no idea what ".dat" format is...
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Forum Post: RE: Converting a existing library to PCELL library
Thanks Andrew. I'm working on the layout part now. I planned to implement the schematic as you mentioned. On the symbol, I just need to write a label about the Vt being used and I can figure it myself. We used to maintain extracted views (av_extracted) for the standard cells in each cell. Now the question is how to achieve that? I'm totally blank here. What would be the best practice? The parasitics will not change with respect to the transistor VT so does back annotating the caps in schematic is a good idea? I'm need help here. Thanks Ramakrishnan
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Forum Post: RE: [17.2] PCB Designer crashes every time DRC is run
Hi Dylan, Apart from what Pat suggested below in his earlier reply, could you try to follow the steps below and see if the crash still occurs when you run the DRC. 1. Go to Setup and User Preferences 2. At the categories section, expand the DRC and select General 3. Check the box for the preference "drc_single_thread" and click Apply and then OK. 4. Go to Display, Status and then update DRC Thanks KCTM
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Forum Post: Orcad Capture - save project as not working
Hi, When pressing on the "save project as" button a blank window with no options appears - see figure below. Any idea how to fix this? I'm using orcad capture 16.6 with a dongle license. Thanks, Amitai
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Forum Post: RE: How to color a string using SKill
Hi Dave Thanks so much for your help. I have an issue now. I have updated my code & testing it in 16.6, it works perfectly fine. We are moving to 17.2 soon, & i was testing it in 17.2, to my surprise its not working at all. Any reason why. Here i captured how the message came out. Is there any extra command needs to be added. Please help. THIS IS HOW I ADDED IN THE FPRINTF fprintf(mcl_log.log " \nFAILED :LINE WIDTH IN PACKAGE GEOMETRY/ASSEMBLY_TOP IS %.3f " width) Below is the message, the whole command is being printed out. FAILED :LINE WIDTH IN PACKAGE GEOMETRY/ASSEMBLY_TOP IS 0.076 FAILED :LINE WIDTH IN PACKAGE GEOMETRY/ASSEMBLY_TOP IS 0.076 FAILED :LINE WIDTH IN PACKAGE GEOMETRY/ASSEMBLY_TOP IS 0.076 FAILED :LINE WIDTH IN PACKAGE GEOMETRY/ASSEMBLY_TOP IS 0.076 FAILED :LINE WIDTH IN PACKAGE GEOMETRY/ASSEMBLY_TOP IS 0.076
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Forum Post: RE: Problem when using RFDE momentum blocks in Cadence (Drop across Resistance w/o any current)
Hi Andrew, 1. The MoM component does not have an option for interpolation method. I just get a warning when running the DC analysis. It says "Risky extrapolation to DC of data given in S-parameter file". I tried the nport from the analogLib with the "bbspice" as the interpolation method and also selecting the option "Extrapolate to DC". The problem still persist and I still see a drop across the resistance connected to the gate. 2. As it takes a long time to simulate, the lowest point is at 80 GHz. Like you suggested, there is no DC point in the file. Is there anything that I could add into the S Parameter file? 3. I did the simulation with linear sweep and a step size of 1GHz. 4. It does not throw any complaint about passivity or causality. Please let me know if you need any other data. Regards Dipal
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Forum Post: Reduce clearances/thermal relief between shapes and clines
Hello, I'm using allegro 16.6 and I'm having some difficulty with clearances between certain shapes: From my screenshot, I'm trying to connect all the areas in red together (they are all RXGND). Is there something I should be using such as global parameters or some box i need to tick for these smd pads to be covered? Cheers, Fraser
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Forum Post: RE: Reduce clearances/thermal relief between shapes and clines
Fraser, I see your DRC's but, what's the violation. What does it say when you click on the DRC mark and do " Show Element". I notice that you have 2 pads real close together around these DRC's. Are they on the same net? If so, you may need to set the Same net spacing for SMD Pins to SMD Pins to something smaller. Cheers Dale
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