Dipal, Well, I think it's a little optimistic for any model to be built which will simulate at DC and in the time domain if the lowest simulation point you ran in Momentum was at 80GHz! How the spectre is supposed to know that the capacitor is open circuit at DC (after all, it doesn't know it's a capacitor - all it has is the s-parameters). I nearly fell off my chair when you said the minimum frequency is 80GHz! A 1GHz step is pretty big too. I'm not sure we can help much more without seeing the data, but to be honest I think the main problem is that the s-parameter data is missing too much low frequency and even high frequency data, plus is too sparse. Andrew.
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Forum Post: RE: Problem when using RFDE momentum blocks in Cadence (Drop across Resistance w/o any current)
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Forum Post: RE: VerilogA issues -- transition function
Yes. you're right, I don't think the transition function would work for what I'm trying to do. This is the first model I'm developing in VerilogA and I'm still quite a novice. Would it be possible to increase the time step size which cadence uses to calculate the two variables? So that it wouldn't evaluate the variables at no less than some minimum time apart? So if I wanted it to evaluate the variables at most every .2 seconds for instance it would evaluate the variable for transient times that are > .2 seconds apart but not < .2 seconds apart? I was trying to use the timer function for this but I'm not sure if this is the right approach.
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Forum Post: RE: Reduce clearances/thermal relief between shapes and clines
Hi, Dale again. Did you try setting your Shape's line width to something smaller under Shape/Global Dynamic Parameters? It looks like the shape in the middle is having trouble filling because of this.. Also, your shape to shape spacing need to be set to allow for what you are doing.
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Forum Post: RE: Problem when using RFDE momentum blocks in Cadence (Drop across Resistance w/o any current)
Hi Andrew, I just finished a simulation and it seems indeed to be a problem with the step size! I reduced the lowest frequency as well. You are right, the S parameter file was having no data at lower frequency range which was causing this silly problem! Thank you so much!! Regards Dipal
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Forum Post: RE: [17.2] PCB Designer crashes every time DRC is run
Thank you Pat and KCTM. Running dbDoctor fixed it. I wasn't exactly sure of the purpose of dbDoctor until now. I did try KCTM's suggestion as well but it did not fix it although this time I do get a error dialog box but it's mostly generic.
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Forum Post: RE: Reduce clearances/thermal relief between shapes and clines
I think your problem is that your shape is just missing the center of the pad by just a tiny fraction. I always use C-Lines to connect the pads, even if the c-line is REALLY small. I'm not sure what spacing I'm looking at here, but taking a 5 mil trace (anything more than 0 really) and connecting the pads directly will remove the rat, and then you can draw the shape on top of that. The other option would be to edit your shape so that it fully covers the center of the pad. It also needs to cover the center point of the C-Line when you connect to the C-Line, or you will have a similar problem there too.
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Forum Post: RE: Declaring global net in schematic composer
Hi, I also have the same requirement. Is it supported in Cadence now ? I need a global net (not a pin) which should be used for many cells. The issue is this net has the following requirement from LVS perspective : All these cells should have this net connected together but floating. So if it becomes a global pin, then the floating requirement is not being satisfied. Regards, Pushan
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Forum Post: RE: Problem when using RFDE momentum blocks in Cadence (Drop across Resistance w/o any current)
Hi Dipal, You might want to take a look at the IMS MicroApp “7 Habits of Highly Successful S-Parameters” is on our Cadence website. On Cadence Online Support , the in-depth AppNote is here: 20466646 . Best regards, Tawna
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Forum Post: RE: Declaring global net in schematic composer
Is what supported in "Cadence" now (there's no tool called "Cadence", so not sure what you're referring to either)? As far as I could see from the earlier old question there wasn't anything that needed implementing in the tools - and it's not clear from your post either. Just because a net is global doesn't mean it can't be floating... Put simply, I don't understand what your problem is. Regards, Andrew.
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Forum Post: RE: skill code to turn on/off grid
Thanks Andrew, pteSetVisible("Grids" nil "Grids") pteSetVisible("Tracks" nil "Grids") doesn't seem to turn off grids which in my case are here: Palette/Grids/Snap Patterns Local Grids/fb1 Global Grids/GFG Can you please take another look? thanks, Kevin
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Forum Post: RE: skill code to turn on/off grid
Kevin, Which version (subversion - Help->About will tell you) are you using? Turning the Grids off should turn them all off. If you want to do it more selectively, you'd do: pteSetVisible("Grids;Snap Patterns;Local Grids;fb1" nil "Grids") pteSetVisible("Grids;Snap Patterns;Global Grids;GFG" nil "Grids") Not this is done with the layout window open - I assume you're doing it then rather than in the .cdsinit? It wouldn't know which technology you're working on otherwise... Regards, Andrew.
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Forum Post: RE: VerilogA issues -- transition function
When you are talking about the time step size which "cadence" uses to calculate the two variables - I've no idea what you are referring to. Which two variables? You've not posted your model so we're all rather in the dark here as to what your code is actually doing or what you want it to do... Regards, Andrew.
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Forum Post: RE: Declaring global net in schematic composer
Sorry for the ambiguous request. I am looking for this in Virtuoso Schematic Editor. Whenever I use "abc!" as wire name and use it for my cell connections, it netlists the same as Global Pin abc! and uses the same for the sub cell connections. I want it to not netlist it as Global Pin but still use it for the sub cells, so that though the nets are connected (same abc!) but they do not become top level Global Pin. Regards, Pushan
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Forum Post: RE: Declaring global net in schematic composer
Pushan, Which netlister? I wouldn't have expected a global net to be netlisted as a pin of a .SUBCKT unless you made it a pin. Please give an example so it's obvious what you're talking about - I could maybe guess, but it's a guess given the information you've provided... Regards, Andrew.
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Forum Post: RE: Declaring global net in schematic composer
Hi Andrew, I used CDL netlisting with Netlisting Mode as Analog. It is not netlisting the "abc!' as the subckt Port but it is putting the following in the CDL out which makes Calibre LVS to recognize it as a Pin : *.Global abc! *.PIN abc! Regards, Pushan
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Forum Post: RE: skill code to turn on/off grid
I'm using ICADV12.3-64b.500.10 I just added these two lines to our equivalent of .cdsinit and it still doesn't work.. I've been putting the commands to the .il file, I showed the hierarchy earlier so that you would know exactly the grid options I'm referring to. thanks, Kevin
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Forum Post: RE: Declaring global net in schematic composer
Finally it's clear what you were asking. There doesn't appear to be any control to stop the *.PIN from being netlisted for each *.GLOBAL net. I'm not sure why it matters - I don't think I've seen any reports about removing this. The one CCR that I found was that you can use the variable simPinGlobals=t which instead of adding *.GLOBAL it will add pins through the hierarchy - although it still outputs the *.PIN at the top level. I don't know whether that's an acceptable alternative. Anyway, if you want different behaviour (other than manually removing the *.PIN line yourself) then you'll need to contact customer support to request control of this in the auCdl netlister, with details as to why it's needed (what goes wrong if this is there). Regards, Andrew.
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Forum Post: RE: skill code to turn on/off grid
Kevin, As I said above, this doesn't work in the .cdsinit because it doesn't know which technology you're using. I thought you wanted something for a bindkey - my apologies. However, from ISR11 there's a cdsenv variable to do something similar - see this article . I think potentially it could be done with a deRegUserTriggers, but I seem to recall that there's a timing problem if you try to do that. So I know it's one subversion above the one you're using, but hopefully you can switch to a later version and try this out? Regards, Andrew.
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Forum Post: RE: Declaring global net in schematic composer
Many Thanks for your help!! Regards, Pushan
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Forum Post: RE: How to color a string using SKill
Hi Jerry, Just add the following line at the start:
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