Or at least to delete all the user defined properties for the schematic symbols in the schematic design.
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Forum Post: RE: Editing the schematic symbol part properties using the TCL command in OrCAD Capture
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Forum Post: TCL code the delete all the user defined properties of all the schematic symbols in the schematic design.
Dear Community, I have few schematic symbols on the schematic design and i have added some user defined properties to all the schematic symbols and i want to delete those user defined properties and only default properties should be there, is it possible either normal method or TCL. If TCL script possible, can anyone let me know the TCL command to be executed deleting the user defined properties of all the symbols. Regards, Deepak G Krishnan
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Forum Post: deNewCellView option to not open the text view in editor
In ocean script we have the following command to create a systemVerilog view. But this command also opens the file in text editor. Is there a way to prevent it from opening the file? deNewCellView(lib_name, cell_name, "systemVerilog", "systemVerilogText", nil) If I create many views via script it just keeps opening so many files.
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Forum Post: RE: Orcad Capture 23.1 won't back annotate from Orcad X / PCB Designer
As it may need data sharing to debug this issue, I will be contacting you through separate channel of communication.
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Forum Post: RE: deNewCellView option to not open the text view in editor
The easiest way to create the view and import it into the library is to use the cdsTextTo5x command (this is a UNIX command - you can type "cdsTextTo5x -help" to see the command-line options. You could then invoke this from SKILL using (say) ipcBeginProcess or even just using system("cdsTextTo5x ..."). Using a Design Editor function when you don't want the Design Editor is a rather odd way of achieving this. If you wanted something that's entirely in SKILL, you could use my code in How to create a text cellview using SKILL (you can pass the viewType as the 5th argument), followed by using vmsUpdateCellViews() to do the analysis of the view to ensure the shadow database etc is created. Regards, Andrew
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Forum Post: RE: Capture Hierarchy- using global power pins for signal nets?
If you place ground symbols instead of ports in a hierarchical block, the hierarchical pins will not get generated. This is because hierarchical pins are used to connect the ports of a hierarchical block to the ports of its parent block, and if there are no ports to connect, there will be no hierarchical pins. Hierarchical ports and hierarchical pins are used to connect the different levels of a hierarchical block to each other.
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Forum Post: RE: Skill-Command for execute printing in the print preview menu
Hello Mabr86 , I could not find any SKILL command which can start printing. We have axlCanvasPrintToPDF() which can be used to save as pdf.
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Forum Post: BlackBox with Assura LVS
Hello, I'm working on the design of a pad ring and the I/O cells have only the abstract view, with no schematic, so I am trying to do a blackbox LVS with Assura (4.1_USR6_EHF13). I created an empty schematic with just the pins (same pins as the abstract) and generated the corresponding symbol. I followed the "Assura LVS Black Box Flow" Application Note and I added the pinLayer definitions in the extraction rules file, before setting the ?blackBoxCell command in the avParameter. I created a text file which contains all the cells that I'd like to black box and launched the LVS. I get the following warnings from the .erc file (just one as example, but I get the same for each black box cell): *WARNING* blackBox - cell 'PDDW0204SCDG abstract tpd018nv_MT2' does not bind to anything *WARNING* 'PDDW0204SCDG abstract tpd018nv_MT2' is marked as a BlackBox cell only in the layout side If I look at the LVS error report, I get something like this. The Layout connection is fine (the signal connects to the I/O cell and to a digital buffer, so 1 NMOS and 1 PMOS gate. The connection seems to be lost in the schematic. = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 3) Schematic Net: nRST S 1 of nmos2v G S 1 of pmos2v G Layout Net: avC47 L 1 of N G L 1 of P G L *1 of PDDW0204SCDG ?{DS I IE OEN PE C PAD} Am I doing anything wrong? Did I miss anything from the App note? Thanks, Stefano
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Forum Post: RE: Editing the schematic symbol part properties using the TCL command in OrCAD Capture
Hi Rohit, I am good, I believe you are also good. Try below tcl code, Property which are not locked by schematic are deleted. set lSession $::DboSession_s_pDboSession DboSession -this $lSession set lNullObj NULL set lStatus [DboState] set lDesign [$lSession GetActiveDesign] set lSchi_Name [DboTclHelper_sMakeCString] set lPart_Name [DboTclHelper_sMakeCString] set lPart_Name1 [DboTclHelper_sMakeCString] set lPrpName [DboTclHelper_sMakeCString] set lPrpValue [DboTclHelper_sMakeCString] set lPrpType [DboTclHelper_sMakeDboValueType] set lEditable [DboTclHelper_sMakeInt] set propnamelist {} if {$lDesign != $lNullObj} { set lSchematicIter [$lDesign NewViewsIter $lStatus $::IterDefs_SCHEMATICS] #get the first schematic view set lView [$lSchematicIter NextView $lStatus] set lPage_Name [DboTclHelper_sMakeCString] while { $lView != $lNullObj} { #dynamic cast from DboView to DboSchematic set lSchematic [DboViewToDboSchematic $lView] $lSchematic GetName $lSchi_Name set lPagesIter [$lSchematic NewPagesIter $lStatus] #get the first page set lPage [$lPagesIter NextPage $lStatus] # puts [DboTclHelper_sGetConstCharPtr $lSchi_Name] while {$lPage!=$lNullObj} { #placeholder: do your processing on $lPage $lPage GetName $lPage_Name # puts [DboTclHelper_sGetConstCharPtr $lPage_Name] set lPartInstsIter [$lPage NewPartInstsIter $lStatus] #get the first part inst set lInst [$lPartInstsIter NextPartInst $lStatus] while {$lInst!=$lNullObj} { #dynamic cast from DboPartInst to DboPlacedInst set lPlacedInst [DboPartInstToDboPlacedInst $lInst] if {$lPlacedInst != $lNullObj} { set lPropsIter [$lPlacedInst NewEffectivePropsIter $lStatus] set lStatus [$lPropsIter NextEffectiveProp $lPrpName $lPrpValue $lPrpType $lEditable] while {[$lStatus OK] == 1} { #placeholder: do your processing for $lPrpName $lPrpValue $lPrpType $lEditable set lPropName [DboTclHelper_sGetConstCharPtr $lPrpName] set lState [$lPlacedInst DeleteEffectiveProp $lPrpName] # puts [DboTclHelper_sGetConstCharPtr $lPrpName] #get the next effective property set lStatus [$lPropsIter NextEffectiveProp $lPrpName $lPrpValue $lPrpType $lEditable] } delete_DboEffectivePropsIter $lPropsIter } #get the next part inst set lInst [$lPartInstsIter NextPartInst $lStatus] } #get the next page set lPage [$lPagesIter NextPage $lStatus] } #get the next schematic view set lView [$lSchematicIter NextView $lStatus] } delete_DboLibViewsIter $lSchematicIter delete_DboSchematicPagesIter $lPagesIter # return $partlist } Please let me know your feedback.
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Forum Post: RE: TCL code the delete all the user defined properties of all the schematic symbols in the schematic design.
Hi RohitRohan, Try below tcl code, Property which are not locked by schematic are deleted. set lSession $::DboSession_s_pDboSession DboSession -this $lSession set lNullObj NULL set lStatus [DboState] set lDesign [$lSession GetActiveDesign] set lSchi_Name [DboTclHelper_sMakeCString] set lPart_Name [DboTclHelper_sMakeCString] set lPart_Name1 [DboTclHelper_sMakeCString] set lPrpName [DboTclHelper_sMakeCString] set lPrpValue [DboTclHelper_sMakeCString] set lPrpType [DboTclHelper_sMakeDboValueType] set lEditable [DboTclHelper_sMakeInt] set propnamelist {} if {$lDesign != $lNullObj} { set lSchematicIter [$lDesign NewViewsIter $lStatus $::IterDefs_SCHEMATICS] #get the first schematic view set lView [$lSchematicIter NextView $lStatus] set lPage_Name [DboTclHelper_sMakeCString] while { $lView != $lNullObj} { #dynamic cast from DboView to DboSchematic set lSchematic [DboViewToDboSchematic $lView] $lSchematic GetName $lSchi_Name set lPagesIter [$lSchematic NewPagesIter $lStatus] #get the first page set lPage [$lPagesIter NextPage $lStatus] # puts [DboTclHelper_sGetConstCharPtr $lSchi_Name] while {$lPage!=$lNullObj} { #placeholder: do your processing on $lPage $lPage GetName $lPage_Name # puts [DboTclHelper_sGetConstCharPtr $lPage_Name] set lPartInstsIter [$lPage NewPartInstsIter $lStatus] #get the first part inst set lInst [$lPartInstsIter NextPartInst $lStatus] while {$lInst!=$lNullObj} { #dynamic cast from DboPartInst to DboPlacedInst set lPlacedInst [DboPartInstToDboPlacedInst $lInst] if {$lPlacedInst != $lNullObj} { set lPropsIter [$lPlacedInst NewEffectivePropsIter $lStatus] set lStatus [$lPropsIter NextEffectiveProp $lPrpName $lPrpValue $lPrpType $lEditable] while {[$lStatus OK] == 1} { #placeholder: do your processing for $lPrpName $lPrpValue $lPrpType $lEditable set lPropName [DboTclHelper_sGetConstCharPtr $lPrpName] set lState [$lPlacedInst DeleteEffectiveProp $lPrpName] # puts [DboTclHelper_sGetConstCharPtr $lPrpName] #get the next effective property set lStatus [$lPropsIter NextEffectiveProp $lPrpName $lPrpValue $lPrpType $lEditable] } delete_DboEffectivePropsIter $lPropsIter } #get the next part inst set lInst [$lPartInstsIter NextPartInst $lStatus] } #get the next page set lPage [$lPagesIter NextPage $lStatus] } #get the next schematic view set lView [$lSchematicIter NextView $lStatus] } delete_DboLibViewsIter $lSchematicIter delete_DboSchematicPagesIter $lPagesIter # return $partlist } Please let me know your feedback.
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Forum Post: virtuoso schematic replace function
Hi everyone! I’ve run into a tricky problem, as follows: I need to replace all the CMOS in the schematic with CMOS from another process technology. However, when using the “replace” function, the default values of the device parameters in the new process CMOS overwrite the parameters of the devices to be replaced. How can I solve this issue? I’ve searched for some solutions before, such as loading a mapping file when using the replace function to declare that the parameters remain unchanged. But there is no option to load a mapping file in the “replace” function window. Is it because the version of Virtuoso I’m using is too old? Besides this, are there any other methods? Best regards
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Forum Post: RE: Pitch in Unsteady FINE/Turbo
Hello, I must be missing something. I already did my mesh with 20 GV blanes and a rotor with 40 blades, but the same error message appears. Where do I specify that I want 1 vane and 2 blades?
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Forum Post: RE: How to get a symbol from sch and paste it into a specified OLB library file with tcl script?
I execute the code. But run to the next step. It gets a NULL obj. SO it fail to continue the script. Capture> set obj [$lLib GetPackage $lNameCString $lStatus] NULL
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Forum Post: RE: [CDF][Parsing error regarding CDF parameter in AMS]
You missed out the important part - i.e. what is inside the block which you've showed as having CDF parameters vdd and value. My guess is that you have a schematic with an instance of a vcvs from analogLib, with the gain set to: (int(value)>>0)&1 (not sure why you would right shift it by 0 bits, but nevertheless). Anyway, the answer is to not use the int() function. If you've declared the addr design variable as an integer on the Simulation→Options→AMS Simulator, Netlister tab, then you don't need to try to convert it to an integer. It seems that this int() and real2int() are convenience functions to round to an integer (I think to support compatibility with spectre) but leave it as a real (for some reason). So if you use: (value>>0)&1 or (value>>1)&1 etc, then this should work (it does for me). If it doesn't work, please show what you're actually doing inside the block in question... Andrew
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Forum Post: RE: [CDF][Parsing error regarding CDF parameter in AMS]
hi Andrew, my bad as I assume the expression is the same as that in Dann's post. and correct I was putting down " ( int ( pPar ("value") ) >> 1 ) & 1 " in that VCVS's gain. I confirm it is the int() which makes this difference. by removing this function, we're now free of those errors. ===== =============== problem posted has been resolved ! ==================== after that unfortunately I got another new error as highlighted below. since there is not much info at this point, I'm still debugging on it. I'd report more details in another new post once enough info collected. before that I've a basic question regarding the Xcelium env. setup (as I thought I might be in wrong direction from the very beginning). may I know what a typical "Xcelium_ROOT" (in 64-bit OS) (similar to CDS_HOME etc.) looks like for "Xcelium 22.03-s005" ?
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Forum Post: RE: [CDF][Parsing error regarding CDF parameter in AMS]
You don't need to do all that messing about with your path. It's sufficient to put ${Xcelium_PATH}/tools/bin in your path and nothing else. The wrappers will take care of choosing the 64-bit version (with CDS_AUTO_64BIT set). I'm not sure that's the reason for the internal error though - hard to know for sure (I'd fix the path and try again). What OS are you running on? (what is contained in /etc/os-release ?) I'd first try using newer XCELIUM and SPECTRE versions (yours are a few years old) and if it still occurs then contact customer support. Andrew
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Forum Post: Sweeping netlist Files (spectre/spice) in the Corners Setup Form
Hello, in the "Virtuoso ADE Assembler User Guide", Chapter 8 (Working with DSPF Files) highlights a way to sweep DSPF files in the corner setup form, which comes very handy to combine different extracted netlists with specific corner sweeps, I am looking for a similar feature but for spectre/spice netlist file to be swept in the corner setup form, I tried the same steps as highlighted for the DSPF files instructions but instead of using the "dspf_include" statement, I used the standard "include" statement, however this did not work as intended, the included file did not have precedence over the defined subckts in the netlist, if there is not similar approach where I can sweep netlist files in corner setup, is it safe to use the dspf_include statement as a workaround with spectre/spice netlists ? or would be there a way to indicate the precedence when redefining the same subckt Virtuoso version IC23.1-64b IC23.1-64b.NYISR5.27 Thanks, Fahmy
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Forum Post: RE: Sweeping netlist Files (spectre/spice) in the Corners Setup Form
Fahmy, The issue is if you have duplicate subckts - which it sounds as if you have both the subckt from the schematic, plus the included subckt via the corners. Model files found by corners are always included from the top of the netlist (there is control whether it's before or after the parameters, but it's always at the top) and hence anything netlisted by ADE will appear afterwards. There is a spectre option duplicate_subckt (which defaults to "error") which controls the behaviour, but if it's not producing an error, the last-defined always wins - so this won't help you. dspf_include is different, because it can use the terminal order from the subckt definition in the main netlist, but the contents from the included DSPF file - so it replaces the contents of the netlisted subckt with the external DSPF data. There isn't a similar mechanism for standard Spectre included subckts. The solution could be to use the hierarchy editor and then mark the blocks you want to include from a model file as "stop points". This means you'll get an instance line but no subckt - and then your subckt can come from your model file inclusion. You need in this case to be careful about the pin order, so you would also need to edit the base CDF (Tools→CDF→Edit) and then ensure that the termOrder in the spectre simulation information matches the order of pins in your external subckt definition. Regards, Andrew
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Forum Post: RE: Tooling holes versus Fiducials - Do I need both?
Hi John, Good points and in particular with respect to the pasting of the board and AOI equipment. So there are multiple moving parts to the assembly process but I think it's good to look at the steps we can control. In Cadence we have the option to create a pick and place file for out boards as we all know. We can generate an X,Y location of footprints based on either pin one or the center of the part. I have always used the center of the footprint. The file generated is based on the board origin and that is the kind of key thing. This would be the home position or 0,0 XY. So the options for the origin might be a fiducal, or a pad or a via and all the other footprints on the board are relative X,Y location to the origin. Over on the SMD Placement side of things today there are many manufacturers such as Juki, Fuji, Panasonic to name a few. There are even low cost machines based on stepper motors for less than 4k USD that can reliably place SMD parts down to 0201 size. For accurate placement of parts the higher end machines use servo motors which are more accurate over travel. All of these machines include optical software. Basic idea is the physical machine can use your X,Y placement file or generate it's own based on scanning the board. Depending on the board size there will always be a slight variation in the actual sixe of the board due to the manufacturing tolerance of the board size. This means that when the board is fed into the SMD placer the origin of the board more than likely will be off. This is where the vision equipment comes in. With the vision equipment provided with the machine all it needs is a viable location that it can use to start placement of the parts. The higher end machines are so fast even doing optical scan in addition to placing the actual parts on the board. The lower end machines can do this also except they are slower dong the scan part. To save on programming time at the SMD line having a good board origin that matches your physical placement file can save an SMD operator alot of time, hence my mention of the marker at that board origin 0,0. People can find out more to get a feel for how the SMD process is done. Youtube has many, many videos. By way of an example of a less costly machine do a search for Neoden smd placer. On the pasting of the board today there are SMD machines that do both. Basically the board comes into the SMD machine and the paste is applied to the pads as a fine blob just like placing a part, then machine proceeds to place it;s parts. On the AOI post SMD placement process, I typically supply as a gerber file the board outline and the physical patds only. Traces silk etc are not needed. Placement file is also used. The A0I as far as I am aware is programmed similar to how the SMD placement machine is programmed but as a seperate process. Over the past 15 years or so there have been huge advances in SMD placement machines. One of the best advances has been in the optical scanning part IMHO. All the best.
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Forum Post: RE: Sweeping netlist Files (spectre/spice) in the Corners Setup Form
Hi Andrew, Thanks for the prompt reply, The solution with the stop points would be challenging to implement as the different sections have include files for different subckts so this would leave me with the dspf_include, do you see any drawback in using dspf_include for standard spectre subckt files ? Thanks, Fahmy
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