Hi, Netlisting fails when using AV_Extracted views for some cells, but not all. The netlist error is: ERROR (OSSHNL-378): Cannot descend into the view 'spectre cmos_sch cmos.sch schematic veriloga ahdl pspice dspf' specified for library 'basic' and cell 'ipin' in the 'View To Use' or 'View list' fields of config '...' for the instance '_qrcPin5' in cell '.../av_extracted_rc_coupled'. Modify 'View To Use' or 'View list' to contain an existing view. The variable 'hnlConfigMissingViewAction' can be set to "warning" or "ignored" to decrease severity Setting the variable does not help. config is set up with template "spectre" opening up the AV_Exracted in layout viewer and searching for the instance gives no results dspf output of QRC does not have this problem, but instance/net names are obfuscated and not usable in parasitic editor. qrc log header: Cadence Quantus Extraction - 64-bit Parasitic Extractor - Version 23.1.1-p051 Thu Feb 15 21:25:45 PST 2024 Any clue what that _qrcPin5 is? Thanks Svilen
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Forum Post: Problem netlisting AV_Extracted from QRC extraction
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Forum Post: RE: Display Your Know How: Placement
B
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Forum Post: RE: Display Your Know How: Placement
None of the pictures. Electrical properties need to be considered.
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Forum Post: RE: Tooling holes versus Fiducials - Do I need both?
Modern assembly SMT equipment that includes vision assist do not need fiducials. The board is typically scanned and each SMT footprint identified as an XY centroid location. Tooling holes may be needed by the fabricator, ask in advance. For a fidicual to be really useful the fiducial should be located at the board origin (0.0), others can be included elsewhere on the board. The reason for the 0,0 location aka board origin is that the pick and place file you provide with your board wont require offset programming in the SMT Software. I had not used fiducals in years. ASSY houses never asked for them either due to the modern vision equipment they use.
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Forum Post: RE: Tooling holes versus Fiducials - Do I need both?
Both of our assembly shops require fiducials. We also include a block-skip fiducial that is blackened out on bad circuits. Our machines see that as a do-not use circuit. Don't assume every shop does not need fiducials.
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Forum Post: RE: Display Your Know How: Placement
A very valid point! Thanks excellon1! A key point here is, what do you prioritise in your typical designs? As PCB designers, we are often forced to be the "middle-person" with the responsibility to choose between often-conflicting requirements. So ultimately the question remains; as a designer what do you consider to be the top priority? Let's see what other designer have to say...
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Forum Post: RE: cline angle
thank u for ur response. yes, it works regards masa
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Forum Post: RE: Tooling holes versus Fiducials - Do I need both?
Thank you for reminding us. Very important.
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Forum Post: Boolean Operations in MarkNet file
Hi everyone, I want to use markNet to check metal that is in the "background". The layer in the attached photo is a metal etch layer, so the background is actually where the metal is. I think I need to create a dummy layer somehow. It looks like "geomholes" may do the trick but I don't know how to incorporate Booleans in the MarkNet file. I would like to click on the background inside the layer shown and the "hole" be used for metal checks. I can use SKILL or assura to generate a dummy layer, place it in the layout and then do the check on that, but I would like to avoid that if possible. Can anyone help me with this? Thanks, Beto
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Forum Post: RE: Display Your Know How: Placement
Planes deliver the best low impedance conductor on your PDN network. Traces always add parasitic inductance. Trace impedance probably won't dominate package impedance of the bypass cap. Looking at PDN as cumulative seems to work. Via-in-pad to a plane delivers the ultimate PDN solution. But, placing plane vias close to device pins is defensible in a design review. https://www.sigcon.com/Pubs/news/9_07.htm https://learnemc.com/decoupling-for-boards-with-closely-spaces-power-planes
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Forum Post: RE: How to get a symbol from sch and paste it into a specified OLB library file with tcl script?
Hi Jaydstone, Please use the below code to copy the cache lib to a new library. Make sure you have provided your library location for copy the packages. set lDestnLibPath [file normalize {C:\Users\Desktop\LIBRARY2.OLB}] this line need to modify according to your OLB loaction. set lSession $::DboSession_s_pDboSession DboSession -this $lSession set lStatus [DboState] set lNullObj NULL set lDesign [$lSession GetActiveDesign] set lNameCString [DboTclHelper_sMakeCString ] set lSrcLibPathCS [DboTclHelper_sMakeCString] set lDesignCacheIter [$lDesign NewCachesIter $lStatus] set lCachedObject [$lDesignCacheIter NextCachedObject $lStatus] set lPartName [DboTclHelper_sMakeCString] #Provide the loaction of OLB in which package should be copied. set lDestnLibPath [file normalize {C:\Users\Desktop\LIBRARY2.OLB}] set lDsctnLibPathCstring [DboTclHelper_sMakeCString $lDestnLibPath] set lDestnLib [$lSession GetLib $lDsctnLibPathCstring $lStatus] # set lContLib [$lCachedLibObject GetContainingLib] # # set llibname [$lSession GetLib $lContLib $lStatus ] while {$lCachedObject != $lNullObj} { set lCachedLibObject [DboBaseObjectToDboLibObject $lCachedObject] set lContLib [$lCachedLibObject GetContainingLib] $lCachedLibObject GetSourceLibName $lSrcLibPathCS set lLib [$lSession GetLib $lSrcLibPathCS $lStatus] # puts $lLib if {$lLib != $lNullObj} { set obj1 [$lCachedObject GetName $lNameCString] set obj [$lLib GetPackage $lNameCString $lStatus] # set obj [$lContLib GetPart $lNameCString $lStatus] # set lGetPartName [DboTclHelper_sGetConstCharPtr $lNameCString] if {$obj != $lNullObj} { # puts $lGetPartName # $obj GetName $lPartName $lDestnLib CopyPackageAll $obj $lNameCString $lStatus # puts [DboTclHelper_sGetConstCharPtr $lPartName] } } set lCachedObject [$lDesignCacheIter NextCachedObject $lStatus] } # $lDestnLib MarkModified $lSession MarkAllLibForSave $lDestnLib $lSession SaveLib $lDestnLib $lSession RemoveLib $lDestnLib delete_DboDesignCachesIter $lDesignCacheIter Please let me your feedback how it goes at your end.
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Forum Post: RE: Problem netlisting AV_Extracted from QRC extraction
Svilen, I found some reports of a similar issue (it seems that something is creating instances of pin cells in the av_extracted view) and in both cases it pointed to something in the libInit.il of either the library you're using or the technology library. Unfortunately in both cases no more detail was recorded (and this was from 9 years ago, so finding out more detail is unlikely to be possible). Probably best to contact customer support over this (submit a case after logging in). Andrew
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Forum Post: Bootstrapped Transmission Gate circuit design
Hi I'm designin a 3 bit binary differential current steering DAC using transmission gate as a switch in the top and the bottom of my circuit. When the transition at MSB is occured, the time of charging and discharging the capacitance is increased which make the transition more slow. In order to reduce Ron and the lower thecapacitance of charging and discharing i need to use bootstrapped Transmission gate in cmos technology; I ask if you can help me to show thye architecture of this Bootstrapped Transmission Gate circuit design. I'm so gratefull if you can help me
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Forum Post: RE: How to decrease the capacitance of charging and discharging at the MSB of current steering DAC
Please do not post the same question in multiple forums (please read the Guidelines for the Custom IC Design Forum ). I've joined your two posts. Andrew
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Forum Post: RE: Tooling holes versus Fiducials - Do I need both?
Very interesting points excellon1, thanks for sharing. Great to hear from other experiences out there! I know that our manufacturing engineers could use a pad or a feature from the board and program that in as a fiducial. There were many disadvantages though. Such as the pad should not get paste on it which can affect the perceived center position, copper exiting the track could also. If the pad becomes covered during placement, then the "fiducial" could no longer be seen by Optical Soldering inspection machines (AOI) or other equipment further down the line. Does your process require those? We would produce some larger pcbs in panel sizes >= 200mm. Tolerance effects over longer distance are accumulative. So if you are producing small pcbs then you will probably get away with some things but for larger pcbs, the pads at either extreme ends of the pcb will be more out of position. The minimum pad pitch on your board will also dictate what you can get away with. Is there more you can tell us about the vision assist you mention and the types of equipment etc?
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Forum Post: [CDF][Parsing error regarding CDF parameter in AMS]
hi all, this should have been appended to another post (+6 years) but let me just create this new one with some updates. basically the problem is exactly the same but this time that solution doesn't work. please refer to the following pictures in which even though design parameter "addr" has been identified as integer, we still got the same errors. maybe it's due to the combination of Spectre/Xcelium versions?
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Forum Post: RE: [CDF][Parsing error regarding CDF parameter in AMS]
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Forum Post: using python scripts for sending axl-skill() api command to cadence
I am new SKILL scripting and Cadence. I want to automate the SKILL scripting flow through python script i.e. it is possible to send commands from python to skill interpreter.Is there is Python-cadence library for support .Can we invoke cadence from Python and send skill commands from python script to Cadence SKILL interpreter.Please suggest.
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Forum Post: Switching from voltage source to high impedance port in VerilogA: Convergence problem
For my VerilogA testbench, I need a port that can act as both a voltage source, and as a high impedance. As far as I know, there are two ways to implement a high impedance, either by assigning a 0 (or very close to 0) current to the port, or using a very high resistor value. (ex: V(port,n)<+I(port,n)*R_big ). Given that there is no way to use a transition while switching between current and voltage source, I went for the second way. The problem is that when switching from a current source to high impedance, I have convergence issues. My code looks something like this: if(write=0) begin temp=I(port,n)*R_big; end else begin temp=A_Value; end V(port,n)<+transition(temp,0,1n); For more context, my ultimate goal is to be able to both charge a capacitor and sense it's voltage, through a transmission gate. Trying the same approach with different simpler circuits, and it doesn't seem to give a problem. I tried adding resistors to help in converging, doesn't seem to help much. Any help would be appreciated. Thank you.
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Forum Post: RE: Editing the schematic symbol part properties using the TCL command in OrCAD Capture
Hai CadAP, Hope you are doing well, Similarity, can we create a TCL code for removing all the properties of all the schematic symbol in the schematic design. Like there are few schematic symbol on the schematic page, I want to remove all the properties of each and every symbols using the TCL command. Regards, Rohit Rohan
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