I create an incremental technology file and library that combines two independent technology files. I will refer to the combined technology file as "techfile_combo" and the two independent technology files as "techfile_0" and "techfile_1". When I compile the incremental technology file, I get a message that everything was successful with no errors. When I create a new library and attach it to techfile_combo, valid layers from techfile_1 do not show up in the LSW, but valid layers from techfile_0 do show up. However, from Skill scripts, I can draw shapes on valid layers from both techfile_0 and techfile_1. And, in manual editing mode, I can select a shape and hit "q" to view its properties, and I can manually change the layer to any valid layer from techfile_0 and techfile_1. But to reiterate, none of the layers from techfile_1 show up in the LSW. Thus, I cannot hide them, isolate their view, click on them to manually draw shapes, etc. Any idea what might be going on?
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Forum Post: valid layers not showing up in LSW
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Forum Post: RE: gmoverid in dc operating point is not equal to gm/id
Hi Andrew, what is the difference between ids and id? Furthermore, is the Vdsat number also given by id/gm on the dc opt point? I notice that Vdsat is not equal to what some designers call V* = gm/id
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Forum Post: RE: Gain of a Charge Pump in Phase locked loop
here's one way: 1. hook up the charge pump output to a zero impedance voltage source to set the Vctrl node. 2. Sweep the input phase difference and run pss for each input phase. 3. Average the output current over a pss period and divide it by the input phase error. 4. You will get a Icp vs. phi curve. The linear slope around 0 defines the small signal gain, but of course, any nonlinearities also matter.
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Forum Post: Set library manager window title with SKILL?
Hi, Is it possible to set library manager window title with SKILL? Best regards, Alex
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Forum Post: How to determine Scaled-sigma sampling (SSS) Number in high-yield estimation (HYE) for SRAM design? Thanks
I am running high-yield estimation (HYE) simulation for custom SRAM design in Virtuoso 6.1.6 ADE XL. The simulation circuit is a critical path which contains representative cells and wire delay models to mimic 512Mb SRAM macro. We do not run a simulation directly on the 512Mb SRAM macro to avoid highly long run-time. In HYE setup, we need to specify the sampling number for Scaled-sigma sampling (SSS) method. According to Cadence technical paper, the default number of samples for SSS is 7000. The problem is, the 512Mb SRAM macro has millions of devices while the critical path has only hundreds of devices. When we run HYE on the critical path, we expect that the hundreds of devices' variations could mimic millions of devices' variations in some way. Assume that the default 7000 sampling number is appropriate for 512Mb SRAM macro's HYE simulation, then what sampling number is adequate for the critical path HYE simulation in order to mimic millions of devices' variations? Actually, I am not even sure if the default 7000 sampling number is adequate when running HYE simulation directly on the 512Mb SRAM macro. I appreciate any suggestions on this problem. Thanks and regards.
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Forum Post: RE: change instance name in schematic
Do you have more than one Instance selected? At the top of the form you see Apply to: all selected Instances of same master While this is possible for most of the parameters, it can't be done for instance names for obvious reasons. The property editor assistance only works on one instance, that is the reason you can make the edit there. I think I saw that in the past. Marc
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Forum Post: RE: Transferring user defined property values between Capture and Allegro PCB Editor
Looks like you have an OrCAD based license and Allegro and OrCAD have a different menu structure so in OrCAD look under Check - Properties and that should get you going.
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Forum Post: RE: change instance name in schematic
Good spot Marc. In fact, even if you only have a single instance selected, and change the Apply To: to "all selected" or "all" it disables the instance name field. That's not the default, so I think it must have been changed by the user to that. Andrew.
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Forum Post: RE: How to determine Scaled-sigma sampling (SSS) Number in high-yield estimation (HYE) for SRAM design? Thanks
7000 should be OK as far as I know - it's the scaled sigma method that supports the extension to high yield, and shouldn't need more samples. However, I'll try to get a more precise answer from R&D. Regards, Andrew.
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Forum Post: RE: Set library manager window title with SKILL?
Alex, No. Why would you want to? Andrew.
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Forum Post: RE: Set library manager window title with SKILL?
It would be nice to add project name to the title. I am doing migration from one project to another. Virtuoso open in two projects and it will help to see project name :)
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Forum Post: RE: valid layers not showing up in LSW
A wild guess without testing this. Do you have the leLswLayers section in the first tech file? One way to check this out would be to do Right Mouse over the layer palette (assuming you're not using a really old version that still had the LSW) - say over the "Valid Used Routing" checkbox area - and pick "Options". There's a choice on the Options form called "Scope of 'All Layers' Layer Set" which can be "LSW layers" or "techfile layers". Try changing it to techfile layers. Either that or you have a Layer Set in place which is limiting what shows up? Note that a lpp doesn't need to be "valid" to create shapes in SKILL - it's only for interactive use. Regards, Andrew.
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Forum Post: RE: Set library manager window title with SKILL?
OK - you'd need to request an enhancement via customer support. I wouldn't say there's a particularly high chance of this being implemented soon though, as I don't think it's been requested before and there will almost certainly be many higher priority requirements ahead of it... (just trying to be realistic here!) Regards, Andrew.
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Forum Post: RE: Set library manager window title with SKILL?
Ok. Understood.
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Forum Post: RE: How to determine Scaled-sigma sampling (SSS) Number in high-yield estimation (HYE) for SRAM design? Thanks
Hi Andrew, Thank you for your reply. Our most concern is, we use the HYE results of the critical path to predict the yield of the 512Mb SRAM macro. The critical path is composed of hundreds of devices while the 512Mb SRAM macro contains millions of devices. we need to make the hundreds of devices' variation space cover millions of devices' variation space in SSS sampling. Intuitively, if 7000 sampling number is OK for the 512Mb SRAM macro, it seems that the sampling number should increase for the critical path. I am not sure. Looking forward to your reply. Have a nice day! Tina
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Forum Post: RE: Unable to map design without a suitable latch. [MAP-3] [synthesize]
Resource sharing has recognized that some math operations in this plan can have the same physical resources for diminished gadget usage. Helpinessays.com
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Forum Post: RE: How to determine Scaled-sigma sampling (SSS) Number in high-yield estimation (HYE) for SRAM design? Thanks
You might also be interested in the article at http://www.deepchip.com/items/0575-02.html where different approaches to HYE and their possible problems are examined.
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Forum Post: RE: change instance name in schematic
Thank you Marc and Andrew! Both of you are correct. Indeed it is the "Apply to: all selected" that is causing the "issue", even if there is only one instance selected. It has been bugging me for a while now. sometimes when I restart cadence, then it is ok, after a while then it becomes disabled. I had no clue what changed, now I know :) Thanks!
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Forum Post: RE: valid layers not showing up in LSW
Thanks for the quick reply! I checked the technology file, and there is a leLswLayers() section in the first tech file. Good guess! This is a foundry provided tech file, and it looks like it was added in their latest version (which explains why this issue mysteriously popped up). I just added a leLswLayers() section to the second tech file with its own layers, and now the issue is solved. Thanks for the help!
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Forum Post: False GLS timing violation being reported from irun for Functional D input in Scan mode
Hi I am running GLS sims for atpg vector, I am getting violation for D input even when ATPG Select (SEL) signal is high and it is TD (test Data) input which matters. Following is the task $setuphold in my Flop model $setuphold(posedge CK &&& RB, negedge D &&& ~SEL, 4.49:4.49:4.49, -1.39:-1.39:-1.39, flag,,,d_CK, d_D); In SDF file the timing check for this flop is (SETUPHOLD (negedge D) (posedge CK) (x:y:z) (a:b:c)) Now if SEL is high violation from D input should not be taken into consideration and be masked as per $setuphold task above. But while scan is happening and D input changes I get timing violations for D input setup time of Flop. Please let me know if you have faced similar issue and what was your solution
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