Hi, I am doing custom layout in Virtuouso & and for that purpose, I'll define some designs (as per standard cell rules) and instantiate them in the upper level layouts. Now, when I instantiate any design in layout, I need to manually align their PR boundary for the neighboring cells. Is there any way to automate this PR boundary aligning process in Virtuoso? Any help will be greatly appreciated.
↧
Forum Post: Auto PR Boundary Alignment in Custom Layout
↧
Forum Post: RE: Transferring user defined property values between Capture and Allegro PCB Editor
Expert advice - who would have thought the same options would appear in different menus depending on your licence configuration! I guess I'll need to put in a feature request to be able to define the position for user-defined properties at the *.dra level - it would be really great to have them appear laid-out nicely, already lined up with the different positions of my rotary dial, rather than just in a big pile on the centre of the symbol. But at least I can make them appear. Thanks again!
↧
↧
Forum Post: ERROR (OSSHNL-109)
Hi, No matter how many times I check and save, every time I try to generate the netlinst I get the below error. Please help me solve this. Cadence Virtuoso version: IC6.1.6.500.1 ERROR (OSSHNL-109): The cell view, 'XXXXX_tb/schematic', has been modified since the last extraction. Re-extract the design (File->Check and Save menu option) for schematic cell views to correct this error. Thanks
↧
Forum Post: RE: Finding symbol and footprint library
\share\pcb\pcb_lib and \tools\fsp\samples\dra For SPB 17.2 Hope it helps.
↧
Forum Post: CPF - two primary_power_nets for one power domain (different virtual power domains for different voltage sites of an IP block)
Hi there! Cadence innovus 16.13 | CPF v1.1 | ST Microelectronic 28nm I am working on a Multiple power domain design. I have got a PLL block as an IP (no access inside the block of course) and this PLL block according to its vendor datasheet consists of two separate domain: an internal analog part with 1.8V an internal digital part with 0.9 I need to put this whole IP block in one domain for instance PD_PLL. However, since there are two separate analog and digital parts in the IP block, no update_power_domain -primary_power_net can be used for the whole PD_PLL. Therefore, I used two virtual power domain in my CPF file. This is an excerpt of the whole lines of CPF file: define_library_set -name lib_0_80V_12t_lvt_lp_tc -libraries AND ALL OTHER LIBRARY SETS define_level_shifter_cell ALL NECESSARY CELLS create_power_nets -nets {VDD_LEVELSHIFT} -voltage 0.80:1.20 create_power_nets -nets {AVDD_PLL} -voltage 1.8 create_power_nets -nets {DVDD_PLL} -voltage 0.9 AND ALL OTHER NETS ... create_power_domain -name PD_PLL -instances ... create_power_domain -name PD_LEVELSHIFT -instances ... # Creating virtual power Domain for analog and digital parts of PLL to assign primary power_nets create_power_domain -name PD_DPLL create_power_domain -name PD_APLL create_level_shifter_rule -name lsr_pad_pllout -pins {ChipTop_1/LevelShiftDomain_1/INFOUT*} -from PD_DPLL -to PD_LEVELSHIFT update_level_shifter_rules -names lsr_pad_pllout -location to create_nominal_condition -name cond_high_lvt_lp_12t_0v80 -voltage 0.80 update_nominal_condition -name cond_high_lvt_lp_12t_0v80 -library_set "lib_0_80V_12t_lvt_lp_tc" and for all other voltages create_power_mode -name PM_0v80 -domain_conditions {PD_SRAM0@cond_high_lvt_lp_12t_0v80 \ create_global_connection create_global_connection -domain PD_PLL -net AVDD_PLL -pins avddpll1v8 create_global_connection -domain PD_PLL -net AGND_PLL -pins agndpll1v8 create_global_connection -domain PD_PLL -net DVDD_PLL -pins dvddpll0v9 create_global_connection -domain PD_PLL -net DGND_PLL -pins dgndpll0v9 update_power_domain -name PD_DEFAULT -primary_power_net VDD_DEFAULT -primary_ground_net GND -pmos_bias_net VDDS_LVT -nmos_bias_net GNDS_LVT # update virtual power domains for PLL update_power_domain -name PD_DPLL -primary_power_net DVDD_PLL -primary_ground_net DGND_PLL update_power_domain -name PD_APLL -primary_power_net AVDD_PLL -primary_ground_net AGND_PLL The problem happens when I want to transfer signals from 0.90V section to a levelshifter for voltage upscaling. after commiting the CPF file, the following come from CPF commit generated report: **WARN: (IMPCPF-2204): Cannot get the primary power net for the power domain PD_PLL, using first power net DVDD_PLL specified in connections as primary power net. **ERROR: (IMPCPF-261): line 735: create_level_shifter_rule lsr_pad_pllout: Cannot insert a level shifter instance to drive a net from power domain PD_DPLL to power domain PD_LEVELSHIFT, with a valid location in power domain to. The valid cell for this rule was not found. Ensure that the location specified in update_level_shifter_rule is identical to the 'valid_location' option specified by define_level_shifter command. How I can assign two separate power domains to different voltage sites in an IP block and later assign them their respective primary_power_nets and avoiding any problem like the above which doesnt let the tool to add the necessary level shifter cells in PD_LEVELSHIFT for upscaling the signals coming from 0.90V part. Regards
↧
↧
Forum Post: RE: Level-shifter cells are removed after placement
I could solve my problem by following the steps mentioned below: 1- The level shifters are defined in the library with a specific vddi and vddo. for HL or LH check and use the necessary (both or one) one in the CPF libraries. 2-Define the level shifter cells with define_level_shifter_cell and use the range as input and output voltage as may be needed and later match the power domains 3-check the create_power_net for the crossing power domains contains the required ranged which has been defined previously in define_level_shifter_cell 4-create_level_shifter_rule and think in advance about the right combination of the defined cells, defined libraries, vddi and vddo in libraries, and finally the location of placement by setting the a correct -from and -to info in this command 5-If using create_level_shifter_rule more than once remember to use update_level_shifter_rules -names -location to force the implementation either for each rule separately or put all similar ones in the same update command good luck
↧
Forum Post: better Free Allegro Viewer - Orcad Lite
Since Engineers need a way to view allegro board files. And the Orcad Lite has more functionality , why not use that. my blog at robspcb.com/blog/ Pcb Designers and Engineers need to be able to view the same database. So , those Viewers that don't chew up a license, are a great deal. The regular Viewer is really limited in functionality , thats where Orcad Lite comes in to serve as a Viewer. Of Course there are a couple of install caveats. One of them, if you already have a license, it would use that up. Made a Batch .bat file as a workaround, that way you can have multiple lite open. Steps: - download Orcad lite - create shortcut on Desktop - download PCBeditorlite_no_license.bat - put on Desktop PDF
↧
Forum Post: Reliable 1206 and 0603 footprints
Hello, I am trying to design a board with 1206 capacitors and 0603 resistors (SMD types both, of course). From \SPB_17.2\share\pcb\pcb_lib\symbols I have tried to use as a basis the 0603rf_wv_12d.dra and 1206rf_wv_12d.dra but as I can these are overloaded with too much text and even vias (?!). Should I use these and edit them to the minimal working configuration? Also in the same folder we can find the 1206.dra -a much more simplified one. In general I have found some free footprints from Snapeda website and this one. These do not seem to be the working fine or even after being DBdoctor'ed I get some errors ( e.g. E- (SPMHDB-181): Design revision 15.x is too old. Must run the batch dbdoctor to uprev.) A last way out would be using the procedures described in K.Mitnzner's book (Chapter8-p.213) and create a new one (by editing an existing one) - though I tried and found this to be the hardest one (I got stuck while Manipulating the assembly outline ). Since I feel I am in a dead end (Allegro's complexity should not be underestimated especially for beginners as me :-) ) are there any suggestions on how to overcome this critical point?! As pointed in the title what would be the most reliable footprint basis to (re)start with? I would appreciate any help! Thanks in advance, Andreas
↧
Forum Post: Node capacitance difference between captab and AC analysis
I want to measure the effective capacitance on a particular node of my schematic ("/net1"). I tried two methods: 1. Using the captab nodetonode option in DC analysis, reading the "/net1" to "/net1" total capacitance from Capacitance Table window. 2. Adding a 1V AC source (V0) connected to the node and running AC analysis. Then get the capacitance vs frequency plot from Spectre Calculator using the formula 1/(2*3.141593*imag(VF("/net1")/IF("/V0/PLUS"))*xval("/net1")). (This is just C = 1/(2*pi*X*f) where X is reactance and f is frequency in Hz). I cannot understand how to interpret the results, because the AC analysis gives me a frequency-dependent capacitance, while the Capacitance Table gives a single number. Is the Capacitance Table value supposed to give me capacitance at limit when f approaches 0 Hz from the AC analysis? The numbers I get are totally different. The AC analysis capacitance ranges from 1 pF to 2 fF for frequency between 1 Hz and 1 THz. But the captab value is 0.076 fF, which is smaller than all values from the plot (it's split into Variable: 0.076 fF, Fixed: 0.0). I don't know what is the most accurate way to measure the effective capacitance on node /net1, and whether any of the results I get make sense. Additional information: ----------------------------- Simulator: spectre Version icfb: 5.10.41 Thank you.
↧
↧
Forum Post: RE: Reliable 1206 and 0603 footprints
It is true that the learning curve for Allegro is steep with it's mixture of menus and forward/backward selection and operations, but once you get the hang of it it is very rewarding since you will be able to do a lot of "powerful/dangerous" things with it. Furthermore, you and your organization can grow with it. I strongly suggests that you search the internet for beginners tutorials and also for the IPC 7531 standard (or recommendations) that will guide you in your efforts to find the dimensions you need. I almost always use the built-in wizard together with my own template to create footprints and then modify them if necessary to suit my needs. For tutorials, there are a few that emanates from the world of academics. They are not always for the latest 17.2 versions, but they are good starters. For up-reving older footprints, you will need to run DBDoctor stand-alone (!) and once invoked, you will be able to uprev an entire library but bear in mind that the File|Open menu does not allow you to enter wildcards such as *.dra or *.pad. You can point to the specific library folder of interest, but the remaining wildcard *'s will have to be entered using the keyboard. If you find a downloadable library, you will anyway have to verify that it is useable according to your organizations requirements. Especially naming conventions for foot prints and pad stacks.
↧
Forum Post: RE: Auto PR Boundary Alignment in Custom Layout
Hi, you could define alignment constraints in the constraint manager ( one of the assistants ) for your instances. These will be followed by Layout XL interactive editing. It's not that easy to describe that here so maybe have a look at the documentation about it. Constraints can be defined on the schematic or the layout side. There are also a bunch of alignment commands available in the layout editor which can do the task quickly as well. Have the Alignment Toolbar active, select your instances and hit the horizontal/vertical alignment icon. Regards, Marc
↧
Forum Post: RE: ERROR (OSSHNL-109)
Hi, please check the cellview properties ( shift-Q) , check the "system" selector on the top and look for the modified and checked counters. Checked needs to equal or larger than modified to be valid for the netlisting. ( see picture ) In some cases I saw problems when people running SKILL code through hooks at cell saving time which manipulates the cellview. Other than that it's hard to come up with a solution without more information. Sorry. Regards, Marc
↧
Forum Post: RE: Compliance current setting in a voltage source.
Yes, Verilog-A is another option, which I tried. Thanks
↧
↧
Forum Post: RE: Integration with matlab
Thanks Andrew :)
↧
Forum Post: Maxima & minima of a signal between two times in output window.
Hi, Is there a way to find maximum or/& minimum of a signal between two times (say t1 and t2) in transient simulation in Virtuosos Visualization & Analysis XL window ? Thanks in advance
↧
Forum Post: Virtuoso crashing on executing mgc_rve_load_setup_file command for big layouts
HI I am trying to execute the following 'mgc_rve_load_setup_file' command in CIW for a batch of cells.( mgc_rve_load_setup_file command is used to generate calibre view from a pex netlist). For that I am using the below skill code. procedure(pex_list() mgc_rve_load_setup_file("calibreview_1") mgc_rve_load_setup_file("calibreview_2") mgc_rve_load_setup_file("calibreview_3") mgc_rve_load_setup_file("calibreview_4") ) I will load the skill file and then the function pex_netlist() is called in CIW window. For smaller cells like flip-flop,inverter etc the calibre view is getting generated. But if I try to generate the calibre view of a larger cell (example cells with more that 10 flip-flops) the virtuoso is getting crashed. What is causing this crash. Please guide me, is anything wrong with the way skill file is being executed. Regards Anand
↧
Forum Post: RE: Virtuoso crashing on executing mgc_rve_load_setup_file command for big layouts
Hi Anand, that function probably belongs to Mentor, you have a much better chance getting this resolved by asking them. Regards, Marc
↧
↧
Forum Post: Create a simple abstract view from layout
Hello, I want to create an abstract view from an existing layout. This abstract view must contain only pins and the prBoundary. Is there a simple way or tool in cadence to do this?
↧
Forum Post: RE: Create a simple abstract view from layout
Hi, we have the abstract generator for that purpose ( calling "abstract" from the commandline ), but calling it "simple"would be an understatement . It reads in your layout and will generate an abstract view. Best place to start is the user guide in the documentation: $CDSHOME/doc/abstract/abstract.pdf which describes the process in a tutorial with an example database which can be found here: $CDSHOME/tools.lnx86/dfII/samples/tutorials/abstract Regards, Marc
↧
Forum Post: RE: Maxima & minima of a signal between two times in output window.
Use the ymax or ymin functions on the output of the clip function. For example: ymax(clip(VT("/out") t1 t2)) where t1 and t2 are your time window limits. Andrew.
↧