Very hard to be certain given that you didn't give any information about what version you're using. You may need to kill off any running cdsfrb_lsf process (note that you should wait until no jobs are running really). Otherwise, I suggest you contact customer support so that we can gather a bit more data rather than me making wild stab-in-the-dark guesses. Andrew.
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Forum Post: RE: Queue list in job policies of ADE
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Forum Post: RE: Need help in writing Skill for routing between two different MOS
Raghu, Well, if you have the instID and termName of the terminal you're trying to locate, then you'd do something like this: term=dbFindTermByName(instID~>master termName) foreach(pin term~>pins foreach(fig pin~>figs center=centerBox(fig~>bBox) centerTopCoord=dbTransformPoint(center instID~>transform) ; now do something with this coordinate. It's transformed to the top level coordinate space. ) ) It rather depends on what you're trying to do and how ambitious you are. The above finds all the pin figures, finds the centre of the figure, and then transforms the coordinate up to the coordinate system of the containing layout. Note I didn't test the code, but it should be OK I think. Regards, Andrew
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Forum Post: RE: The creation of customVia failed
Adam, There isn't any SKILL support (as far as I know) for creating instances of such cdsGenVias. I found a few CCRs saying this and this is still a project to be completed. No plans to complete it either... I think they're relatively rarely used as a consequence. Regards, Andrew.
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Forum Post: RE: saving results with same net names of two different cells
Zubair, You probably (if you're using ADE L, you didn't say) have to do Results->Save after the first run to save the results under a different name, and then run the second simulation. You can then plot the signal from the second simulation, and use the results browser to navigate to the saved simulation results, and then subtract that. If you do this, the latest run with be picked up by virtue of being "in context", whereas the expression for the saved results will include the directory path for where the simulation data is located. Regards, Andrew.
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Forum Post: RE: variable $freq in veriloga
My latest version is MMSIM 15.10.803 As you say it might be a bit fussy as your example does work, but my current experiment is not working although it might have worked briefly before I made some edits. Is there any documentation or mention in a release note for this $freq feature? Also I haven't been able to probe veriloga internal variables in AC simulation but I can for dc or tran. Thanks, Robin
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Forum Post: RE: variable $freq in veriloga
Hi Robin, The fact that it is not documented tells me that it's not really fully released yet - because it only works in narrow cases. Even then, it's not going to work in time-domain analysis. I wouldn't expect you to be able to probe the variables either because that's not something that can be done in ac analysis (similarly you can't access device operating point parameters during an ac analysis). Maybe I shouldn't have given the "working" example ;-) Probably makes most sense to open a case with customer support so that we can take a look at specifically what you're trying to achieve and then assess how ready the capability is (or isn't) with R&D. Regards, Andrew.
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Forum Post: RE: variable $freq in veriloga
Hi Andrew, This should give an idea of what I was trying to do - a low pass with variable roll off rate. In my simulations it had a flat frequency response of 1. Regards, Robin `include "discipline.h" `include "constants.h" // low pass filter with 3dB/octave roll off // module low_rolloff2(sigin, sigout); input sigin; output sigout; electrical sigin, sigout; parameter real F0 = 10M; // cutoff //parameter real rolloff = 0.5; // 1 = normal RC, 0.5 = 1/sqrt(f) etc real FreqGain; analog begin //FreqGain = 1/(1+pow($freq/F0,rolloff)); FreqGain = 1/(1+sqrt(abs($freq/F0))); V(sigout) <+ V(sigin)*FreqGain; end endmodule
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Forum Post: RE: variable $freq in veriloga
p.s. If I make the output a current and connect output to a resistor load then I get something that looks like the expected behaviour.
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Forum Post: RE: How to short a net and a shape on layout using VIA
Hello Francesco Might I suggest that you do not use Net Short to fool the PCB nets. Doing this will mean that your netlist from the schematic does not actually reflect what is on the board. If you have multiple Ground Planes, such as VSS, AGND, PGND etc on the schematic and your intent is to have them joined on the board then a good way to accomplish this is by using zero Ohm resistors between those nets at the schematic level. On your board you will then have basically a component joining in the ground planes and your board will electrically match the schematic. You could even make a Small copper ground plane part with two pins and a similar schematic Symbol to do the net joining. A good rule of thumb on any design is, If it does not exist on the schematic then it should not exist on the board. Thanks Paul.
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Forum Post: Generating Gerber RS274X In 2:3 Format & Gerber File Syntax Issue.
Hi, I have a couple of issues with exporting gerber data from Orcad/Allegro PCB Editor (16.6) & (17.2) My first issue pertains to exporting the gerber files in a standard 2:3 Format. I work in mils and trying many combinations of database accuracy I have found no way to export in 2:3 positional format. I am wondering if it is even possible ? Looking in the help file 2:3 does appear to be supported. I keep getting a dialog box popping up saying. ( For Raster Artwork Formats Accuracy must be at least one greater than the database accuracy) If my database accuracy is set to 0,1,2 etc I can export without issue using a 2:5 Format but not 2:3 My second issue pertains to the actual syntax of the generated Gerber file. I have a commercial CNC mill that I use for quick RF Proto type boards. Basically the software used with the mill converts the Gerber data to G-Code. That mill software works without issue with many different cad packages that create Gerber files including Altiumn, P-Cad, Mentor etc. It also works with Gerber editors such as cam350 etc. Using the native RS274X data exported from Orcad PCB editor results in un-usable data. In checking the Gerber export syntax from Orcad/Allegro I have isolated the issue. Here are the details. Opening the Gerber file in a text editor shows the following after the GO4 statements in the Header of the file. G04 ================== end FILE IDENTIFICATION RECORD ====================* %FSLAX25Y25*MOIN*% <<<<<<< Issue I with this line The first line ( %FSLAX25Y25*MOIN*% ) indicates that the format of the Gerber file is 2:5 and that the units are in inch. In looking at the Gerber specification and other Gerber output from various cad packages It looks like Cadence has combined this line into one. Normally it should read like this. Or should I say the other tools I have put the info out like this. %FSLAX25Y25*% %MOIN*% As you can see there are two separate lines. One indicating the Format & one indicating the Units. If I edit the cadence gerber file to look like this then my CNC package has no issues reading the data. My question. Is there a template fle available that I can edit so that cadence puts out RS274X gerber in the above syntax ? just like other cad tools. Thanks Paul.
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Forum Post: RE: Set a permute rule with SKILL
Thanks Andrew
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Forum Post: RE: how to create the filled shape for selected Finger?
Hi, you could try this code: axlDBCreateShape( car( axlPolyFromDB( Finger )), t, "Substrate Geometry/outline")
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Forum Post: RE: The creation of customVia failed
Hello Andrew, that's bad news, but thank you very much for clarification! I'll try to find out why this rare method is used. Best regards, Adam
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Forum Post: [IC6.1.7] Simulating VHDL-AMS
I am trying to perform a simple simulation with a VHDL-AMS modeled resistor. Unfortunately I cannot simulate it. I made the following: Created a new Cell View in the Library Manager with the type VHDLAMSText Added the VHDL-AMS Code to the file and saved it via File->Extract Created a symbol for the resistor (resp. Virtuoso created that automatically) Created a new Cell View in the Library Manager with the type schematic Added a simple test circuit in the schematic (One source and my resistor) Switched to the simulator and added "ideal" to the Switch View List in the Environment options Tried to create the netlist Simulation->Netlist->Create Unfortunately the following error occurs: Netlist Error: Cannot find any info on instance "I1" in cell-view "fh_hall_elements" "test" "schematic" Netlist Error: Some cell-views used inside this block could not be netlisted in analog context The element I1 is my resistor. Any ideas on how to resolve this error? Code of the resistor: library ieee, std; use ieee.std_logic_1164.all; use ieee.electrical_systems.all; use ieee.mechanical_systems.all; use std.textio.all; use ieee.math_real.all; entity myres is port (terminal p1, p2: electrical); end entity myres; architecture ideal of myres is constant R : real := 10.0e3; quantity v across i through p1 to p2; begin i == v/R; end architecture ideal;
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Forum Post: RE: variable $freq in veriloga
For this purpose, you could also try to use the fracpole component. For more information, type "spectre -h fracpole" at the command line. The article at http://www.designers-guide.org/modeling/suite.pdf has some additional background information. I have not actually tried this myself so far, so if you try this and it works for you, I would appreciate a short note.
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Forum Post: RE: [IC6.1.7] Simulating VHDL-AMS
First of all, you didn't mention which simulator you're using - but from what you've said, it can't be "ams" (which is what you need if using a Cadence simulator and want to simulate VHDL-AMS models). It can't be ams because if using ams you'd have to have a config, and then Setup->Environment doesn't show the switch view list any more. I'm assuming you're trying to simulate with spectre as the simulator, and this does not support Verilog-AMS or VHDL-AMS - primarily because the "MS" bit means "mixed-signal" and hence you'd need some digital engine in the simulator. So you need to use "ams" (AMS Designer) as the simulator; if you do that, you'd need to create a config view and set the view to use (or switch view list) there (AMS requires you to use a config created in the hierarchy editor). Regards, Andrew.
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Forum Post: RE: encounter SEGV internal error (with optDesign -postRoute)
If you are getting a stack trace, and don't have any obvious errors earlier in the run that you can fix (check your complete log file first), then you need to file a service request so R&D can take a look.
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Forum Post: RE: Innovus Common UI
try report_resource
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Forum Post: RE: [Voltus] set_pg_library_mode command option -power_pins?
See the Power Grid Library Generation chapter in the Voltus User Guide. Commands should work in Innovus.
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Forum Post: RE: SOC encounter: short drc error on a particular cell
Turn on cell blockages in Innovus to see why it thinks there is a short. The blockages in the cell LEF may be more general than the actual cell layout.
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