Thanks for the comments here. Very much appreciated. To confuse things further with detail ... what we actually want to do is add a new sheet in the middle of an existing schematic with new circuitry and keep to the naming convention. Then not rip up any existing circuits when we move to layout. In a 3 sheet schematic we want to add a new sheet 2 and make the previous sheet 2 now sheet 3 and the previous sheet 3 now sheet 4. So … existing 200 - 299 ref des will move to 300 - 399 and the existing 300 - 399 to 400 - 499 so I can use the 200 - 299 for the new circuit on sheet 2. Any way I look at this I can’t seem to keep the layout untouched.
↧
Forum Post: RE: Annotating Ref Des in schematic yet not impacting Layout parts
↧
Forum Post: RE: Convergence problems using analogLib switch (DC simulation)
Hi Pedro, There are a few things wrong: Assuming your en_sine, en_pulse, en_step are supposed to be "active high" (so 0 is disabled, 1 is enabled) the switch (relay) components have the control connections upside down. This is because you rotated the component by 180 degrees. That means the control signal is either 0 or -1.5V whereas I think you want them to be 0 or 1.5. You can see this because the 3rd and 4th connections appear to be the wrong way around with 0 (ground) being the third connection. You have the vt1 values as 3V which means that the relay wouldn't have been fully switched even if they were connected up the right way around. I think you should have vt1=0 and vt2=1.5 on the switch/relay components I wouldn't use such a small on resistance value - that's not good for convergence. Don't use anything lower than 1mOhm You should add a resistor (1Tohm is fine) from stimuli to ground to ensure there's a path to ground. Normally this is done for active devices, but this helps with convergence when the switch is off. Here's what I changed in the netlist: W0 (sine stimuli net05 0) relay vt1=0 vt2=1.5 ropen=1T rclosed=1m W7 (pulse stimuli net06 0) relay vt1=0 vt2=1.5 ropen=1T rclosed=1m W8 (step stimuli net07 0) relay vt1=0 vt2=1.5 ropen=1T rclosed=1m Rl (stimuli 0) resistor r=1T With that, it works well. What you were seeing was that everything was turned on. Regards, Andrew.
↧
↧
Forum Post: RE: eyeDiagram() vs. Measurement --> Eye Diagram trigger period
Generate the Eye Diagram with the assistant, then having plotted it, select the Eye Diagram and use Right Mouse->Send To->Calculator. You'll see that this generates an expression using edgeTriggeredEyeDiagram(). Regards, Andrew.
↧
Forum Post: RE: Meaning of the "Event Time" in Direct Plot form of Pnoise Jitter
It's worth reading /tools/spectre/examples/SpectreRF_workshop/JitterAN.pdf. Normally the noise (and hence the jitter) is in a 1Hz bandwidth (so noise in V/sqrt(Hz) and so jitter would be in s/sqrt(Hz)). Since the noise across the bandwidth of your circuit is all going to produce jitter, you want to integrate the noise/jitter across that bandwidth to find the total jitter. Given that in the jitter analysis you shouldn't be sweeping beyond half the PSS fundamental (otherwise the ideal sampler I mentioned earlier causes the noise to be folded by the sampler and hence double-counted (or more)), you probably just want to use the same frequency range as your frequency sweep in the pnoise analysis. Regards, Andrew.
↧
Forum Post: RE: Generating shapes of overlap of two layers within multiple hierarchies
Quincy, Consider a top cell top_cell, a sub cell sub_cell, and object to be copied id_obj (the outcome of dbGetOverlaps() ) Copying figure from sub_cell to top_cell can be done as follows: cv_sub = dbOpenCellViewByType( 'LibraryName 'sub_cell "layout" "maskLayout" "r" ) cv_top = dbOpenCellViewByType( 'LibraryName 'top_cell "layout" "maskLayout" "r" ) id_obj = dbGetOverlaps(cv_sub bBox lpp 32) dbCopyFig(top_cell id_obj list(dx:dy "R0" 1.0) ) if you want to have them exactly on top of copied object in sub_cell, then dx:dy is 0:0 Regards, Taher.
↧
↧
Forum Post: RE: Generating shapes of overlap of two layers within multiple hierarchies
[quote userid="300084" url="~/cadence_technology_forums/f/custom-ic-skill/38428/generating-shapes-of-overlap-of-two-layers-within-multiple-hierarchies/1354235#1354235"]dbCopyFig(top_cell id_obj list(dx:dy "R0" 1.0) )[/quote] should be dbCopyFig(id_obj top_cell list(dx:dy "R0" 1.0) ) Regards, Taher.
↧
Forum Post: Void in Place Bound Layer
I'm trying to create a void in the Place Bound layer so that I can create a 3D representation of a hole through a mounting plate, but Allegro is telling me I can't add voids in that layer. Does anyone know of a work-around? I tried the XOR and ANDNOT shape operations, but I couldn't seem to select the round shape inside the plate outline that was meant to be the hole. See pic attached. Any thoughts?
↧
Forum Post: RE: Convergence problems using analogLib switch (DC simulation)
Hi Andrew, Thanks for the comments. I had rotated the relays indeed. Now I have everything correctly wired, but the net stimuli has all the signals added together (everything on) To debug this, I removed the label stimuli from all the three relays and replaced them with sine_o, pulse_o and step_o. Probing these nets show that, despite the relay being open, the waveform passes to the output of the switch. Shouldn't the 1Tohm resistor kill the signal ? Is there a way to kill a voltage source when I don't need it. I had enable variables inside each source, forcing the voltage to be 0 when I wanted it disabled, but I am not sure that this is the right approach. In the screenshots below, you can see that I've removed the label stimuli, and even that way, the signal shows on the "output" of the switch. In the figure below, I was expecting to see the sine output only and not the others since the switch is open. community.cadence.com/.../netlist_5F00_1.txt Thanks for your time. Best regards, Pedro
↧
Forum Post: RE: Meaning of the "Event Time" in Direct Plot form of Pnoise Jitter
Thanks a lot Andrew.
↧
↧
Forum Post: RE: Generating shapes of overlap of two layers within multiple hierarchies
Taher, Er, that won't work. The output of dbGetOverlaps is a list of objects or a list of lists - with information about the hierarchical path down to each object. You'd have to: Loop over this list to copy each object using each piece of "overlap" data. Work out the overall transformation - using dbGetHierPathTransform for example - you've just used a fixed transformation which won't be correct if there is more than one level of hierarchy, or rotation. Get the leaf object from the "overlap" info - fairly easy to find . Then dbCopyFig that with the overall transformation (for each "overlap"). Using the abe functions is easier than all of this, so if you have access to an IC617/ICADV123 release (ideally probably later than ISR5-6 - there were some issues with the "abe" functions in early IC617/ICADV122 versions which resulted in a change of the how the arguments are passed). Regards, Andrew.
↧
Forum Post: RE: Void in Place Bound Layer
Can you not use the new STEP model functions inside Allegro? If not then draw a shape similar to below, make the grid small and then the line that goes to the edge won't effect too much.
↧
Forum Post: RE: Convergence problems using analogLib switch (DC simulation)
Pedro, You haven't swapped vt1 and vt2 (the Open and Closed voltage) - you have the Open Voltage (vt1) at 1.5 which means that a high value (1) for your en_sine, en_pulse and en_step parameters will mean that those sources are disconnected (proviso below - they are weakly connected) whereas when they are at 0, they are strongly connected. So either swap the two values or your enables are active low. The proviso is that when you disconnect each source to step_o, sine_o, pulse_o, there is no load (they are open circuit). So you either have the source connected to the node via a 1m resistor or a 1Tohm resistor - in both cases the voltage at the end of an open circuit is going to be the same as the input source. If you added (say) a 1k resistor to ground on the sine_o, pulse_o and step_o nodes, then you'd see the signals changing correctly depending on the state of the relay. Regards, Andrew.
↧
Forum Post: RE: Void in Place Bound Layer
I'm using 17.2 so I have access to the STEP model mapping, but unfortunately I don't have access to a company-approved application for creating the STEP model, and the vendor doesn't have a model either. I guess I'll try your work-around, but I need to put 6 holes in the plate - perhaps I can create a template "hole" shape and copy it into an array of solid shapes. Not sure why Allegro is preventing voids. :-(
↧
↧
Forum Post: RE: Request - Skill script for block level floor planning (Constant area stretch)
I appreciate all the help, I noticed that command in the drop down menu, but never knew how to use it. Thanks again.
↧
Forum Post: RE: OrCAD16.6 DRC check problem: "Net has two or more aliases"
Hi, Edit the symbol to change the pin type to 'Passive'. This makes the pin name no longer a signal alias.
↧
Forum Post: RE: Convergence problems using analogLib switch (DC simulation)
Hi Andrew, I swapped vt1 and vt2, as you said, re-named en_pulse, en_sine, en_step back to "stimuli" and hanged a 10k resistor from "stimuli" to ground. And .. it is working now :-) Thank you very much for your help. Best regards, Pedro
↧
Forum Post: RE: Void in Place Bound Layer
You could define two shape, add an arc on the edge and place them next to each other. You can even have them overlap if the arcs are a little tricky to add to the edge. If you don't want to play with adding arcs to the edge you could define the shapes on Etch/Top and use Void Circle to create the edge arcs than just Z-Copy the shapes to Place_Bound_Top. It is a workaround but at least it gets you what you want. :-) Not sure why there is a limitation with having voids in the Place Bound shape. Hope this helps, Mike Catrambone
↧
↧
Forum Post: constraints: MIN_METAL_SPACING and MECH_PIN_TO_CONDUCTOR_SPACING
I'm having trouble locating these constraints. I want to change the hole to everything spacing to 30 mil. I did it in constraint manager but when I update the dynamic planes the spacing is still 8 mil. The mechanical pins do not have any constraints associated with them.
↧
Forum Post: RE: Void in Place Bound Layer
I tried creation on the copper layer and then Z-copy to Place Bound, but it threw away the void. Not sure if I'm doing it incorrectly. Abutting shapes with arcs worked, so I guess that's the winner. I think I'll submit a feature change request for the lack of voiding on Place Bound.
↧
Forum Post: RE: Post layout simulation using Ocean Script
Hi Dimitra, Yes, I have included the extracted view and included it in the 'Switch View List' as you mentioned. As far as i have understood and verified till now is that when you include the extracted view and run the simulation, then it will include the Parasitic information( RC information related to layout) in the netlist itself. That means the netlist that has been generated after including the extracted view has not only the design information but also the Resistor and capacitor information associated with each node. So, for doing post layout simulation, we don't need to write any extra command in our ocean script,as netlist has already information about the parasitic. And When you run the simulation, netlist keep on modifying itself. Please correct me if i am wrong somewhere. As you have mentioned "design( LibName CellName ViewName) ".Yes i have used it too earlier to generate the netlist of design without opening the GUI view of design. I was wondering if there is any ocean command that generate the netlist after including the extracted view, without opening the GUI view?? Regards, Ishant Anand
↧