Dear All, My schematic consists of a dc voltage source and a simple resistor written in verilogA, just to understand how to use verilogA files with Virtuoso ADE. The netlist from Virtuoso ADEL -> Simulation -> Netlist -> Display is as follows: // Generated for: spectre // Generated on: Mar 23 01:58:58 2018 // Design library name: labs // Design cell name: testing_verilogA // Design view name: schematic simulator lang=spectre global 0 // Library name: labs // Cell name: testing_verilogA // View name: schematic V0 (net2 0) vsource dc=1.2 type=dc I0 (net2 0) resistor_verilogA r=1 simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ checklimitdest=psf dc dc dev=V0 param=dc start=0 stop=1.2 write="spectre.dc" oppoint=rawfile \ maxiters=150 maxsteps=10000 annotate=status modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile save I0:in saveOptions options save=allpub ahdl_include "/home/sv376/Cadence/AHDL_stuff/resistor_verilogA/veriloga/veriloga.va" After running the dc simulation, the error in my Virtuoso CDS.log window is: ERROR (ADE-3036): Errors encountered during simulation. The simulator run log has not been generated. Possible cause could be an invalid command line option for the version of the simulator you are running. Choose Setup->Environment and verify that the command line options specified in the userCmdLineOption field are supported for the simulator. Alternatively, run the simulator standalone using the runSimulation file in the netlist directory to know the exact cause of the error. So I went to my netlist directory from my terminal and used the ./runSimulation command. The resulting output is as follows: Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. User: sv376 Host: en-ec-ph314-10.ece.cornell.edu HostID: FD80C911 PID: 31974 Memory available: 6.5414 GB physical: 16.5123 GB Linux : Red Hat Enterprise Linux Server release 7.4 (Maipo) CPU Type: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz Socket: Processors [Frequency] (Hyperthreaded Processor) 0: 0 [3576.1] ( 4 ), 1 [3850.0] ( 5 ), 2 [3856.1] ( 6 ) 3 [3949.8] ( 7 ) System load averages (1min, 5min, 15min) : 1.2 %, 1.9 %, 2.9 % Hyperthreading is enabled Simulating `input.scs' on en-ec-ph314-10.ece.cornell.edu at 1:59:53 AM, Fri Mar 23, 2018 (process id: 31974). Current working directory: /home/sv376/Cadence/labs/testing_verilogA/spectre/schematic/netlist Warning from spectre. WARNING (CMI-2015): Unable to open log file `../psf/spectre.out'. Success. Reading file: /home/sv376/Cadence/labs/testing_verilogA/spectre/schematic/netlist/input.scs Reading link: /opt/cadence/mmsim Reading file: /opt/cadence/MMSIM151/tools.lnx86/spectre/etc/configs/spectre.cfg Reading file: /usr/include/stdc-predef.h Reading file: /home/sv376/Cadence/AHDL_stuff/resistor_verilogA/veriloga/veriloga.va Reading file: /opt/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.vams Reading file: /opt/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/disciplines.vams Time for NDB Parsing: CPU = 46.849 ms, elapsed = 127.028 ms. Time accumulated: CPU = 58.888 ms, elapsed = 127.031 ms. Peak resident memory used = 31.4 Mbytes. The CPU load for active processors is : Spectre 0 (30.8 %) 1 (7.7 %) 2 (7.7 %) 4 (7.7 %) 6 (8.3 %) 7 (9.1 %) Other Error found by spectre during AHDL read-in. ERROR (VACOMP-1024): Unable to create directory input.ahdlSimDB/ (775) ERROR (VACOMP-1024): Unable to create directory input.ahdlSimDB//.resistor_verilogA.ahdlcmi/ (775) ERROR (VACOMP-1024): Unable to create directory input.ahdlSimDB//.resistor_verilogA.ahdlcmi/Linux/ (775) ERROR (VACOMP-2252): Cannot open file: input.ahdlSimDB//.resistor_verilogA.ahdlcmi/Linux/resistor_verilogA.lst - C-code will not be generated !!! Reading link: /opt/cadence/mmsim/tools.lnx86/spectre/etc/ahdl/discipline.h Reading link: /opt/cadence/mmsim/tools.lnx86/spectre/etc/ahdl/constants.h Time for Elaboration: CPU = 19.989 ms, elapsed = 25.1319 ms. Time accumulated: CPU = 78.993 ms, elapsed = 152.279 ms. Peak resident memory used = 38.1 Mbytes. Aggregate audit (1:59:53 AM, Fri Mar 23, 2018): Time used: CPU = 79.1 ms, elapsed = 152 ms, util. = 51.9%. Time spent in licensing: elapsed = 14.6 ms, percentage of total = 9.56%. Peak memory used = 38.2 Mbytes. Simulation started at: 1:59:53 AM, Fri Mar 23, 2018, ended at: 1:59:53 AM, Fri Mar 23, 2018, with elapsed time (wall clock): 152 ms. spectre completes with 4 errors, 1 warning, and 0 notices. At this point, I have tried web searches and the forum and to see how to resolve 'unable to create directory ....' errors that occur above. Why is spectre unable to create the above directories? How can I resolve this issue? I appreciate any help I can get. Thank you! Regards, Krishnaa
↧
Forum Post: Spectre simulation of verilogA file
↧
Forum Post: RE: constraints: MIN_METAL_SPACING and MECH_PIN_TO_CONDUCTOR_SPACING
In Constraint Manager, Analyze>Analysis Mode(s), Design, General is where these parameters are located.
↧
↧
Forum Post: RE: Spectre simulation of verilogA file
Krishnaa, Most likely this is either a UNIX permission problem (not so likely given that ADE managed to create the netlist, unless there are some strange permissions in the netlist directory) or a UNIX disk space or quota issue. Try doing the "runSimulation" again, and if it produces the same errors (maybe you've freed enough space in the meantime) try (with your working directory as the netlist directory) doing: "mkdir someDirectory" and seeing what happens. It's really extremely likely to be a UNIX level problem and nothing to do with the simulator itself. Regards, Andrew.
↧
Forum Post: RE: Annotating Ref Des in schematic yet not impacting Layout parts
You have to rename ALSO on allegro side the components before read the new schematic. If R200 becomes R300 in schematic, rename in allgro R200 to R300. Tip: if R300 already exist in allegro, it will be automatically renamed to someting else in order to not have twice R300 which is impossible from allegro's point of view. Doing this, if it remame it, say, R888; you can not know that R888 have to be renamed to R400. So start rename first FROM the higher refdes (exemple: if higher is actually R887, rename it R987) TO the lower one to avoid it. Of course, have a copy of your boad before starting: a wrong manual change can occure...
↧
Forum Post: RE: Void in Place Bound Layer
For the 3d you can try FreeCAD (it's free) to make models yourself or look at 3dcontentcentral.com, they have many free STEP models. I raised an enhancement request for voids in place bound shapes. CCR number 1453867 but its currently set to inactive.
↧
↧
Forum Post: Multifile combined or Unix command execute in skill code
Hi, Anybody can tell me if skill have a command to combine multi-file? I produce several .txt report file by using skill. It is better to combine them, then compare. I know how to combine them in Unix by command, but how to do in skill? Or I can execute Unix command in skill code? Please help me, thanks in advance. Regards, Jason
↧
Forum Post: Noise Figure of LNA with an input tone (using hb/hbnoise)
Hi all, First of all, I am using version MMSIM 13.11.176 and Cadence IC6.1.6-64b.500.14. I have the following question: I want to simulate the Noise Figure of an LNA by applying an RF tone (frf=1.575GHz) at input and running hb/hbnoise analyses (the power of rf tone is kept small i.e. Pin=-50dBm to get similar results as having a small signal analysis, like SP simulation). So, I am setting up hb+hbnoise as shown in the figures1 &2 . The problem is that when I plot the noise figure from hbnoise results I get an extremely high peak at exactly the frequency where the RF tone is. (Note that left and right of the peak, the noise figure is exactly the same as what I get from the SP simulation.) Is it something that I am doing wrong in the setup of hb/hbnoise and/or measurement ? Regards
↧
Forum Post: RE: Noise Figure of LNA with an input tone (using hb/hbnoise)
There's no need to apply a large signal input for the RF signal when computing the noise, unless you are trying to investigate the effect of a large-signal blocker on the noise response (e.g. if the blocker is driving the circuit into saturation, or you want to look at how the noise intermodulates with the large signal applied). In this case because your RF input is very small, there's no need to have the signal. What is happening is that the flicker noise at DC (which would be infinite) mixes with the RF input frequency resulting in a very large signal at that frequency. You'd see the same at any multiple of any of the large signal frequencies in the circuit. Regards. Andrew.
↧
Forum Post: RE: Noise Figure of LNA with an input tone (using hb/hbnoise)
Hi Andrew, Thanks for the response. Exactly, my intention was to check the Noise Figure of LNA in the presence of a large-signal blocker. I agree with you about the mixing of flicker noise and RF input frequency. But, if you see the document in SpectreRF Workshop, LNA Design Using SpectreRF (MMSIM 13.1, September 2013), Lab2, pages 29-35 where the same simulation is illustrated, the noise figure result does not show this effect. Any ideas why is not showing up there? Is it related to the number of steps in sweeping ? Regards
↧
↧
Forum Post: RE: Noise Figure of LNA with an input tone (using hb/hbnoise)
Yes, you'll notice the the step in the pnoise sweep misses the 2.4GHz point - there's one at 2.125GHz and one at 2.5GHz. Far enough away from the peak at 2.4GHz to see the peak. That said, using a 0.2GHz step also doesn't show the peak because spectre shows: Warning from spectre at freq = 2.4 GHz during HBNOISE analysis `hbnoise'. WARNING (SPCRTRF-15037): Infinite flicker noise is ignored. I don't get it even if I take a very fine sweep near the frequency point (I'm using a much newer spectre though, so maybe that's why it's really omitting it; or the models I have in the workshop may not really model flicker noise). I'm sure it's the reason though... Andrew.
↧
Forum Post: RE: Post layout simulation using Ocean Script
By netlisting the extracted view then it creates the netlist with all RC information so yes you don’t need an extra command in your ocean script. If I understand your question correctly, you can use the createNetlist() ocean command to generate the netlist. To make sure the extracted view is taken into account you need to use the ‘switchViewList arg inside envOption() and include the view there - like you do in ’Switch View List’ in ADE . An example is shown below: envSetVal("asimenv.startup" "projectDir" 'string "./mySpectreExtrNetlists") ;; to set the location where you want the netlist to be created simulator( 'spectre ) design( "ether_adc45n_sim" "adc_sample_hold_sim" "schematic_diffGainAcGainBW") modelFile( '("/sprt/scratch/dimitra/RAP_workshop_616/WORK/tech/GPDK045/gpdk045_v_3_5/gpdk045/../models/spectre/gpdk045.scs" "tt") ) envOption( 'switchViewList list("spectre" "cmos_sch" "cmos.sch" "schematic" "av_extracted1" "veriloga") ) createNetlist() Regards, Dimitra
↧
Forum Post: RE: Annotating Ref Des in schematic yet not impacting Layout parts
This is what I was thinking we needed to do and I appreciate the tip. I was hoping there may be a feature I was missing but renaming before net listing is the only way and it makes sense. Thanks Kevin
↧
Forum Post: RE: eyeDiagram() vs. Measurement --> Eye Diagram trigger period
Yes, that's what I want - works great ! Thanks !
↧
↧
Forum Post: RE: Noise Figure of LNA with an input tone (using hb/hbnoise)
Thanks Andrew, So I assume, I can ommit this effect by selecting in hbnoise all the sidebands except the one that folds the flicker noise inside my band of interest. So, the setup of hbnoise is like that: Regards
↧
Forum Post: RE: Noise Figure of LNA with an input tone (using hb/hbnoise)
Yes, but then you're omitting all noise contributions from baseband which get unconverted. Not sure that's necessarily wise. You could just step over the problematic point... I am a bit short of time today otherwise I'd have tried doing experiments with different versions or trying to get to the bottom of why it doesn't show up with the workshop LNA if I choose a sweep which gets close to the RF input. Andrew.
↧
Forum Post: RE: Noise Figure of LNA with an input tone (using hb/hbnoise)
Sure. Okay, Iif you find time to check that it will be really helpful. Thanks!
↧
Forum Post: Save and Recreate TrackPattern
Hi, i would like to know if it is possible to save trackPatterns from one cellview and copy/recreate them in another cell view. I found the skill scripts that are provided by cadence (such as CCSsaveTrackPatterns.il CCScopyTrackPatterns.il), unfortunately they do not restore/save all attributes (such as trackPattern width for example). From the skill reference i was not able to determine how to access the additional attributes currently not handled by the scripts...so how could it be done? Best regards, Markus
↧
↧
Forum Post: RE: cutClass of vias through skill code
BTW, I did file CCR 1898684 with some suggestions on how to improve the documentation for dbCreateVia - I agree, it's a bit lacking in detail. Regards, Andrew.
↧
Forum Post: Indago tcl commands
Hi, Anyone knows where I can find tcl commands supported by Indago debug analyzer app
↧
Forum Post: test please delete
test moderator please delete
↧