This is something that has bugged me for a while and I have not yet found a solution: we often re-use schematics in the form of modules. Typically, we create the module following a procedure similar to the one described here and, in most of the cases, the result is acceptable if a bit ugly. What I mean is that the symbol created automatically is often very messy, with pins scattered more or less randomly, apart for the convention "inputs on left, outputs on right, I/O on top". As I say, in most cases I prefer not to touch anything but sometimes it is necessary to rearrange the ports in the symbol, and this is where headaches start, because if I move the ports, I am very likely to get the dreaded error "S chematic has port but port does not exist in the symbol. Either delete this port from the schematic or add this port in the symbol. " Even though all I have done is move the ports around, not add/remove anything. The procedure I am following at the moment is this (Allegro 17.2-2016): - generate the module using tool > generate view . This produces a symbol that I can re-use but very messy from the graphical point of view - tools > library tools > part developer: open the cell I just created, and go to symbols > sym_1 , click on the Symbol Pins tab - from here, I click on Edit in Symbol Editor , which opens a new window - in the symbol editor I can, in principle, drag the ports around. However this is where things go wrong, for some reason. In particular, it seems the issue is with ports named like XXX_N . They are automatically created with the bubble that indicates a "active low port". If I try to move any of them (drag them), I can save the symbol but when I try to place it again, I will get the error mentioned above. Can anyone shed some light in what is the correct procedure to move ports in the symbol created from a module using the generate view functionality? Shall I not use _N for naming pins? Am I supposed to use a different program to edit the symbol? As always, any help is greatly appreciated.
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Forum Post: Move ports in symbol created for module
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Forum Post: RE: How to read label inside a particular instance and check its connectivity with the label of another instance
Hi Garima, You may use dbGetOverlaps(..) to get at the shapes in the master cell that are overlapped by your metal routing, the below SKILL expression returns a list of those shapes: (foreach mapcar sl (dbGetOverlaps cv routingRect~>bBox '("Metal1" "drawing") 1:1) (cadr sl)) Assuming there is the parent/child relation between label and shape you can then get at the corresponding labels with the shapes children attribute. This approach works for a routing shape which is a rectangle only - in case of more complicated shapes like pathes or polygons you'd have to turn those shapes into rectangles (dbLayerTile() does that...) first and then do the above for each resulting rectangle.
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Forum Post: RE: Move ports in symbol created for module
As a workaround, I have gave up with the idea of having ports named XXX_N. It seems that whenever a port is named like that, Allegro tries to do something clever. unfortunately, this cleverness results in being impossible to do any modification on the symbol. As soon as a port is touched, I get an error. It is worth noting that Allegro also automatically translates the name of those ports to XXX_* (i.e. the _N is replaced by a _*). I do not knot if this is the cause.
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Forum Post: RE: Monte Carlo Simulations of Extracted Layout
Hi, Does this error pop up in the beginning , middle or end of the postlayout simulation? Once you click on the "Close" button in the pop-up form, what errors you get in the Results tab? Select one of the errors and then do RMB. If "Output Log" is there can you have a look for errors there and possibly share that part of it? To answer your last question, you can run MC simulations having both schematic and extracted views together. Regards, Dimitra
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Forum Post: RE: searching a list of sublists for matching expression
If you have no idea about the list structure (how many nesting levels etc...) I think you need to recursively walk through the list in question...try this one: (defun searchList (theList regex "lt") (let (sublists result) (if (exists el theList (stringp el) && (rexMatchp regex el)) then theList else sublists = (setof el theList (listp el)) (while sublists result = (searchList (car sublists) regex) (when result sublists = nil) sublists = (cdr sublists)) result) ))
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Forum Post: RE: using auto-vias through SKILL
I have used viaGenerateViasAtPoint(), viaGenerateViasFromShapes() and viaGenerateViasInArea() interchangeably for the same task, but i am still facing issues and to my surprise, the time required by the task using these three functions is same, 15-20 seconds. I have contacted support too, but not much help. Is there any other way of putting auto vias from bBoxes, or shapes or area, or any other thing? Regards, Leo
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Forum Post: RE: Monte Carlo Simulations of Extracted Layout
Thank you for your prompt response. Error started in the beginning of the simulation. I understood that I have forgotten to include libraries in the the Model Library in the ADE XL. Now that I included them, I ran the simulation successfully. Thanks!
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Forum Post: RE: How to continue execute a skill script after a form popup in layout ?
Andrew, I don't quite understand why this works...cdnshelp says hiEnqueueCmd ( ) executes after returning from the current function which is self_allign(). However self_align() doesn't return any time before the blocking leHiAlign() returns. So what exactly does hiEnqueueCmd and when is executed?? thx Max
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Forum Post: check spacing between nets with Diva DRC - Net tracing with Diva - Need inputs
Hi, I am writing a diva drc deck to check for space between two nets (not shapes) A net can have a bunch of shapes that are connected. I tried the below way to do this, - trace the nets Net1_name and Net2_name. - compare drc() between them drcExtractRules( m1 = geomOr("M1") via1=geomOr(via1) ... ... upto top metal ;connect all shapes geomConnect( label( ("m1" "label") m1) via(via1 m1 m2) label( ("m2" "label") m2) via(via2 m2 m3) ... up to top metal ) ;get the shapes that belong to the required net netm1 = geomGetNet(m1 "Net1_Name") netm2 = geomGetNet(m2 "Net2_Name") .... upto top metal fullNet1 = geomOr(netm1 metm2 ...) netm1 = geomGetNet(m1 "Net2_Name") netm2 = geomGetNet(m2 "Net2_Name") .... upto top metal fullNet2 = geomOr(netm1 metm2 ...) ;compare drc between them saveDerived(drc(fullNet1 fullNet2 0<sep<10) "DRC error") ) Problem with this approach is that it takes way too long to run for a big cell even though the nets I am looking for a very small. I found that the connect statement is the one that seems to take a lot of time as it tries to connect the whole layout which is not necessary. Any suggestions on how to do this in an efficient way. Thanks, Naveen
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Forum Post: RE: searching a list of sublists for matching expression
thanks so much for your reply, great examples! I'm dealing with sublists that are a little less structured than my simple example, and I should have made the example strings longer. My sublist fields may vary, the number of field that matches the string may vary, and the string is a partial match. I that case, I suggest the following: > mylist='(("one" 1) ("two" 2) (3 "buckle") (_ 4 "my") (_ _ 5 "shoe")) (("one" 1) ("two" 2) (3 "buckle") (_ 4 "my") (_ _ 5 "shoe") ) > setof(list mylist rexMatchList("e" setof(l list stringp(l)))) (("one" 1) (3 "buckle") (_ _ 5 "shoe") )
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Forum Post: RE: Placing large amount of parts
Delete any documentation layer objects like you would any other objects. Enter the dimension environment to delete dimensions. Just ensure that you don't save your dra after compiling the psm.
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Forum Post: RE: Allegro Context Menu Disabled(grayed out) after update to QIR5
It is due to the disabled 'desktop composition' of the windows performance settings. If you enable it, the RMB menus are not greyed-out. I hope there will be a fix for this....
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Forum Post: RE: Jumper & Single Side PCB's
These are steps that I came up with that will work using any size zero ohm SMD resistor and wire jumpers combined. Note when you design is finished your schematic will match your board as well. Plus you will have a BOM containing jumpers too. Pre-requisite- You will need to build package symbols for you various thu hole jumper lengths. Your schematic library must contain wire jumper symbols plus, zero ohm SMD resistors various size ratings R0805, R1206 etc 1. layout your board as if it was double sided. But route all your traces and the bottom side except to hop over another trace or traces. Just drop a via and route a small straight path on top side. The trace length should be as long as your planned jumper. Drop another via to return to the bottom side to finished the route. You can also drop a temporary jumper part over the top route to check clearances and to note what jumper you will add to the schematic later. The jumpers can be a wire or SMD part. 2. Once your board is finished you need to update your schematic. Note. Make sure all your schematic changes are in and board is up to date before doing the following.- Add into the nets in series either jumper or SMD resistors matching the layout. To maintain a user assigned net name like "GND" between each jumper you will need to follows- Rename each segment between the jumpers similar like GND, GND(A), GND(B) etc. By doing this you will be able to search/high-lite by net name. Type GND* to see the whole GND net etc. 3. Generate a netlst. 4. Import into your layout. Do not check "Allow etch removal removal during ECO". This will help you to identify what jumpers go where. This process is a little confusing at first because the etch segments will take on new net names because of the jumpers and show errors. To correct this. In your select filter turn on CLine segs and Vias. In general edit mode detached each route ends one at a time. Place your jumper and reattached to the existing dangling route by routing to it. The route will take on the new net name and the errors will go away. The attached is a typical single sided design that I did a while back. It took longer to layout than to update it with jumpers. That process will take maybe a couple of hours to do. But, its well worth it. I have done this many times in OrCAD and other tools as well. Same process basically. Please note the micro and the net names for the GND nets. It shows the multi GND names as mentioned above. Cheers, Good luck.
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Forum Post: RE: Jumper & Single Side PCB's
These are steps that I came up with using zero ohm SMD resistors and wire jumpers combined. This is not the OrCAD process. Note- when your design is finished your schematic will match your board as well. Plus you will have a BOM containing all the jumpers too. Pre-requisite- You will need to build package symbols for you various thu hole jumper lengths. Your schematic library must contain wire jumper symbols plus, zero ohm SMD resistors various size ratings R0805, R1206 etc 1. layout your board as if it was double sided. But route all your traces on the bottom side except to hop over another trace or traces. Just drop a via and route a small straight path on top side. The trace length should be as long as your planned jumper. Drop another via to return to the bottom side to finish the route. You can also drop a temporary jumper part over the top route to check clearances and to note what jumper you will add to the schematic later. The jumpers can be a wire or SMD part. The wire jumper on top while all SMDS on the bottom. 2. Once your board is finished you need to update your schematic. Note. Make sure all your schematic changes are in and board is up to date before doing the following.- Add into the nets in series either jumper or SMD resistors matching the layout. To maintain a user assigned net name like "GND" between each jumper you will need to do the follows- Rename each segment between the jumpers similar like GND, GND(A), GND(B) etc. By doing this you will be able to search/high-lite by net name. Type GND* to see the whole GND net etc. 3. Generate a netlst. 4. Import into your layout. Do not check "Allow etch removal removal during ECO". This will help you to identify what jumpers go where. This process is a little confusing at first because the etch segments will take on new net names because of the jumpers and show errors. To correct this. In general edit mode, select filter turn on CLine segs and Vias. Detached each route ends one at a time. Delete the vias and top side route too. Place your jumper and reattached to the existing dangling route by routing to it. The route will take on the new net name and the errors will go away. 5. Completed design -MFG output. Generate only files of the bottom side of the board as well as any layers you think you need. The drill chart and the NC files may state PLATED holes. That needs to be addressed by changing the pads on fly to non-plated. However, the latest version of OrCAD have removed the ability to do this easily. BUG here, Cadence is addressing. So just add a note to your fab drawing stating non-plated for all hole for the supplier. The attached is a typical single sided design that I did a while back. It took longer to layout than to update it with jumpers. That process will take maybe a couple of hours to do. But, its well worth it. I have done this many times in OrCAD. Please note the micro and the net names for the GND nets. It shows the multi GND names as mentioned above. There are SMD jumpers on this design too. The SMD resistors us R for the REF designations because they are just resistors. The wire jumpers can be what ever you like. Cheers, Good luck.
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Forum Post: Using Encounter/ Innovus , need parasitic information layer wise information.
Pretty much the title, I have a requirement of getting the layer wise parasitic information. Is there a utility or an option in the gui that allows me to get extraction for specific nets or specific layers? Thanks a ton, this community has been really helpful.
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Forum Post: RE: using auto-vias through SKILL
Hi Leo Do you have a case or CCR number from your local Cadence support? Best regards Quek
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Forum Post: RE: using auto-vias through SKILL
Yes, i have. They are looking into the matter, the R&D team.
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Forum Post: RE: Is there a way to describe the charge across the device as a function of voltage?
I tried using the ddt function. I think that's what you were suggesting. The ddt function seems to be giving me a value of zero even if the argument is not a constant. Below is the code followed by the graphical results captured by the ADE. The polarization variable (blue) is changing while ddt_polarization (red) is constant even though I would suspect that it should be the derivative of the polarization variable.
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Forum Post: RE: How to read label inside a particular instance and check its connectivity with the label of another instance
Hi Garima, To be very clear , you are searching for a command or algorithm in ASSURA RULE WRITING to find whether 2 pins ( not exactly pins,only the labels are placed over the routing layer ) are connected not? You can find the direct command in ASSURA RULE WRITING to trace the connectivity for a label, but am not sure if there is any command or algorithm to find the connection between two labels with routing layer. If anyone can help, it will be very helpful for me too. Thanks & Regards, Amar
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Forum Post: Plotting BJT operating point parameters for DC sweep
Hello, I am using cadence 6.1.6 and I am trying to save BJT operating point parameters such as gm, ft, beta etc during a DC sweep. I saw some cases on community forum and inserted below lines to my save.scs file and sourced it in Setup -> Simulation Files -> Definition file: save Q0 :: oppoint but in the result browser I don't see dc-dc folder although it is present in my psf directory. Can you please help me with this? Thanks.
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