We have some dummy devices in our analog layout. The current LVS processing ignores them, regardless of if they are existing in both layout and schematic. However, the LVS is not clean because of Unbound an Unmatched Pin Errors. Is it possible also to filter out the pins of such dummy devices in order to have the LVS clean? Thanks, Pietro
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Forum Post: LVS filter pins in layout
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Forum Post: RE: PSS not completing in post extraction design
It didn't work with the first solution of setting Legacy RF RCR as a post-layout preset mode. Switching to another version is not possible, as that is given by institute. I am trying to run it on a machine with greater RAM as of now.
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Forum Post: RE: Plotting BJT operating point parameters for DC sweep
Hi Nandish, I see "::" , is that a typo? Can you make sure you use ":" ? If you cannot still get the oppoint then it might be because the BJT is subckt. If that's the case then you need to include the subcktName in the save statement e.g save Q0.subcktName:oppoint. You can find it in the netlist, at the part where the BJT is instantiated. Or it might be because BJT is not located at the testbench level so you need to include the hierarchical path e.g save I0.Q0: oppoint You can have a look into the spectre.out log file and check for warnings, they might give a clue what the problem is. Also, look inside the dc folder in Results Browser to see if the oppoints are there. Regards, Dimitra
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Forum Post: RE: spectre solver for veriloga
Hi Andrew, I have tried with the breakpoint option, but only got even worse results. However if we specifically add more points in PWL file to make the transition time (e.g. 0v-3.3v) from 20ns to 3ns, we can get the results we want. Should the "Breakpoint" option force the simulator transient faster? Cheers, Yuanqi
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Forum Post: RE: Plotting BJT operating point parameters for DC sweep
Also, make sure you don't use spaces (correct syntax: save Q0:oppoint) Regards, Dimitra
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Forum Post: Metal routing not getting extracted
Hi! Some of the metal routings are not getting extracted during QRC extraction. I have a screenshot of av_extracted view to explain my problem. As can be seen in the image, some part of metal is not getting divided into rectangles i.e. not getting extracted into resistors and capacitors. I am doing RC extraction with max fracture length as 5 squares, full chip all nets and resistance mesh disabled. In filtering tab, I have chosen the option to merge parallel R and set Min R to 0.001 Ohm. How to solve this? If I copy that particular metal routing in another layout window without rest of the blocks, it does get extracted. https://drive.google.com/file/d/1rWelJKhneXaUqtdh6Morx3MTG9Q0MSOx/view?usp=sharing Thank You.
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Forum Post: RE: Metal routing not getting extracted
Hi Praveen, Can you share your QRC command-file as well? The Metal1 shapes that are extracted and not extracetd - are they at the same level of hierarchy in the layout? I noticed you are looking at Metal1 pin in the layout layer palette. Typically, in extracted view, the extracted shapes are written into purpose 'net', so can you check what you see in Metal1 net? Regards, Saloni
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Forum Post: RE: Metal routing not getting extracted
This is the command file (also added in answer). The shapes that are getting and not getting extracted are in the same heirarchy. I am sorry, but I did not understand the last point. In the extracted view I just have pins for every layer in the palette. I didn't understand how to check what I see in Metal1 net (or drw - drawing?) https://drive.google.com/file/d/1g_yEiW0dg6qJb6pssnVpHlYfNkOKcQkj/view?usp=sharing #-------------------------------------------------------------------------------------- # OPTION COMMAND FILE created by Cadence Extraction Quantus QRC UI Version 15.22-s247 #-------------------------------------------------------------------------------------- capacitance \ -decoupling_factor 1.0 \ -ground_net "/gnd!" extract \ -selection "all" \ -type "rc_coupled" extraction_setup \ -array_vias_spacing auto \ -max_fracture_length 5 \ -max_fracture_length_unit "SQUARES" \ -macro_cells_type "default" \ -max_via_array_size "auto" \ -net_name_space "SCHEMATIC" filter_cap \ -exclude_self_cap true filter_coupling_cap \ -coupling_cap_threshold_absolute 0.01 \ -coupling_cap_threshold_relative 0.001 filter_res \ -merge_parallel_res true \ -min_res 0.001 input_db -type assura \ -design_cell_name "cc_r3sw_metres_3 layout sgb25_schem_lay" \ -run_name "lvsrec" \ -directory_name "/data/ee15s015/userP/cds/LVS" \ -format "DFII" output_db -type extracted_view \ -cap_component "pcapacitor ivpcell SGB25_dev" \ -cap_property_name "c" \ -enable_cellview_check true \ -include_cap_model "false" \ -include_parasitic_cap_model "false" \ -include_res_model "false" \ -include_parasitic_res_model "false" \ -res_component "presistor ivpcell SGB25_dev" \ -res_property_name "r" \ -view_name "av_extractedrc5" output_setup \ -temporary_directory_name "lvsrec" process_technology \ -technology_corner \ "default" \ -technology_library_file "/data/ee15s015/userP/cds/assura_tech.lib" \ -technology_name "SGB25_dev" \ -temperature \ 27
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Forum Post: [URI] RelXpert support for HISIM_HV model cards.
Hello All, I am implementating an aging model using the URI for a transistor techonology using a HISIM_HV model card. The implementation works fine when I run the simulation using the Spectre Native option, but when I try to do it using RelXpert, the tool produces an error stating that model level is not supported. It seems that the mistake comes when RelXpert parses the Netlist, even before the simulation begins It is there any information regarding what Model Cards types are supported by RelXpert, or if the Model cards should be define in a specific manner, so RelXpert can use it. Like I said before, the implementation works perfectly with Spectre Native reliability Block. Thanks in advance for your help Best Regards, Fabio
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Forum Post: RE: Metal routing not getting extracted
Hi Praveen, Okay I just noticed that you are already displaying all used layers, and everything in extracted view is in pin layer. Even if you don't see the shape divided into rectangles, its parasitics should still have been computed. If you query the big shape you think has not been extracted, you should see a net name in the 'Connectivity' tab, can you confirm? Also, what is the length of this big rectangle? Is there any reason why you want to set the fracture length to 5 squares (the default is microns). This will increase the size of your extracted view and netlist. We typically leave the fracture length to its default of 'inifinite' and let Quantus QRC decide how it needs to fracture the shapes, unless of course there is a reason for changing the default. Thanks, Saloni
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Forum Post: Can't generate netlist in orcad capture CIS
Hi everyone I'm looking for a format/standard/help document that how to form a netlist fie can be imported to orcad pcb editor for a developing program I wanted to get a sample from my circuit, but when I go tools , the create netlist is grey. I tried a fulladder circuit but function still not available ((( Is there anything else I need to do to activate the function? if anyone can help me get a document about the format of netlist I will be even happier thanks for listening to my problem
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Forum Post: RE: searching a list of sublists for matching expression
great examples both - thank you! rexMatchList was handy. I only have one level of hierarchy, but the recursive search example is much appreciated.
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Forum Post: addStripe command for multiple power domains
Hello, I have multiple (6) power domains in my design. I am placing stripes using the addStripe command but every time I am ending up with a design in which the rails are extending outside the selected power domain. Please see attached screenshot. To resolve the issue, I have tried most of the options, like using -over_power_domain, area {x1 y1 x2 y2} etc. Please see my below code modifyPowerDomainAttr PD_1 -box 24 44 56 76 -gapEdges {20 20 20 20} selectObject Group PD_1 addStripe -max_same_layer_jog_length 8 \ -stop_x 56 \ -stop_y 76 \ -width 4 \ -over_power_domain 1 \ -nets VDD_CORE1 \ -start_x 24 \ -start_y 44 \ -set_to_set_distance 5 \ -spacing 1 \ -merge_stripes_value 0.068 \ -layer M2 \ The screenshot shows the PD_1 power domain in which you can see VDD_CORE1 extending over and above the power domain which is not what I want. Apart from this last used code, I have used other variations but end up in which the VDD_CORE1 (the power rail in this case) extends over the entire design. Other times, the entire design is flooded. Please assist me in this and let me know where I maybe going wrong. Thanks, Kashif
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Forum Post: RE: Can't generate netlist in orcad capture CIS
You need to make sure you are at the top of the project folder. If you are on a schematic page view you can not generate the schematic... Can you post a screen shot of the trouble?
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Forum Post: Image Rejection of IQ mixer
What is the easiest way to simulate image rejection of an I/Q downconversion mixer - if possible with pss/pac? Suppose the mixer is a black box with a PORT at the LO input (which generates 0 and 90 degree versions), a PORT at the RF input and two baseband outputs. I can now use pss with the LO as beat frequency and set pac=1 for the RF input port. With PAC I am sweeping from LO to LO+someOffset .... which makes a tone at the upper sideband. After downconversion, I should get signal energy in both I and Q channels. In MATLAB (or a measurement) I would look at DFT(bb_i + j*bb_q) and read off the difference between the upper and lower sideband peaks. But in Spectre I am confused: I can use dB20(leafValue(mag(v("/vodi" ?result "pac")) "harmonic" -1)) and dB20(leafValue(mag(v("/vodq" ?result "pac")) "harmonic" -1)) to get the pac outputs but they are somewhat already in frequency domain. How do I combine them properly to read off the image rejection? Or is there an easier way altogether?
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Forum Post: RE: via connection quandary
Hi John, Here is a picture, verify you have enough clearance between your shape and vias ! Regards Paul.
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Forum Post: RE: Metal routing not getting extracted
Hey! I used the fracture length of 5 squares to show the difference between extracted and non-extracted part. Initially, I was using infinite microns fracture length but then I wouldn't be able to show you the difference. Both give the same results though. The parasitic resistance should be around 600 Ohms but it is just 400 Ohms. To see why this was happening I reduced the fracture length and realized that, that space is not getting extracted in a way similar to other routing. Length is 240.843u and width is 1.26u. Parasitic resistance should be in order of 17 Ohms for that rectangle (the one not being extracted). Total should be around 20 Ohms but since only a part of it is extracted it shows 3 Ohms as parasitic resistance. Including all rectangles I should get 600 Ohms of parasitic R. If I query the big shape in layout view of the design, then in connectivity tab I don't see any net name. I didn't add any net name. Here is the screenshot for this. https://drive.google.com/file/d/1Lv35hjv9YxQvDTE-pChJA0SopYUt45ub/view?usp=sharing Thanks.
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Forum Post: RE: Verilog A ADC design
Thanks, Sir. That solved the problem. Can you say how did you create the 10-bit bus for the 10-bit output? I am facing some difficulty in doing that.
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Forum Post: RE: Metal routing not getting extracted
Hi Praveen, It will be difficult to debug this issue further without looking at the data, so I suggest you contact customer support. Regards, Saloni
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Forum Post: Make synchronous copy(not clone) from cadence SKILL
I have a code which auto stacks Source/Drain of the FET transistors. Lets say i have made this procedure named "STAK". Lets suppose i run this procedure STAK to run over a FET having 5 Sources and 5 Drains. STAK runs and creates 5 individual shapes (M1,V1,M2,V2,M3), lets call them GROUP, for auto-stacking for each of the source and drain. My requirement is to make each of this GROUP( which consists of M1,V1,M2,V2,M3) to be in a synchronous copy with other GROUP for all Sources/Drains of the FET. Thanks and Kind Regards, LEO
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