Hi, I am using virtuoso to simulate my 30k gates design and in the process i am saving all the signals along with power signals. After 2.5ms (2.27 %) of the simulation, i am getting a fatal error " FATAL (SPECTRE-7035): write error on PSF file: Error detected in psf library while writing to file `tran.tran'." and the simulation gets terminated. The simulation folder has >200GB memory available and the size of file tran.tran is 1.5GB. Please suggest how to correct this error. Thanks in advance.
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Forum Post: Error detected in psf library while writing to file `tran.tran'.
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Forum Post: RE: Error detected in psf library while writing to file `tran.tran'.
Hi, This error typically indicates insufficient diskspace but you mentioned that this shouldn't be an issue. Can you share your simulation log (spectre.out)? Regards, Saloni
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Forum Post: RE: How to quickly find device category?
Hi Andrew, I am new to the community.cadence.com, many thanks to you as your solutions for different users queries are helped me a lot. Please help me to get solution for below query, Can we get list of cells under specified Category - MOSFETS (which has again a subcategory branches, like CMOS, DEMOS..etc)of a library. And I tried with ddCatFindCat, ddCatGetCatMemers commands, but failed to get cells if MOSFETS has many inner recursive subcategories. Thanks and regards, Basavaraj Tambur
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Forum Post: COMPONENT FLEXIBILTY IN PART EDITOR OF ORCAD CAPTURE
HIII Guys...I hv a small query regarding orcad capture symbol editor..As i create any SYMBOL the pins are not moving smoothly though i uncheck the SNAP TO GRID option in the settings..I disbale the GRIDS option too and tried other things but unable to resolve the issue..The pins of any IC i am creating doesnt moving smoothly...
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Forum Post: RE: COMPONENT FLEXIBILTY IN PART EDITOR OF ORCAD CAPTURE
Why would they? The theory is: Pins are on the grid in the Part, the Part is placed on the grid in the schematic and, therefore, wiring to the pins does not involve any challenge requiring "exact" placement to make connections. You could make things a lot harder with some more effort.
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Forum Post: RE: straight line (best) fit using viva calculator
Hello Andrew I use positively this function and it is great ! Thank you very much !
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Forum Post: PADS Translator of PCB and Library loose all the swappability info
I have done some test and seems that Pad Translator loose any swappability info of the components. It generate always 1 gate containing all the pins. Also all the pins are NOT swappable. the sama appens from the translation from ALTIUM. Is there a way to receive the correct device.dev. ???? Also when i try to translate the PADS Library the translator loose all the Gate definitions inside the filename.p Any suggest?
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Forum Post: PADS Translator of PCB and Library loose all the swappability info
I have done some test and seems that Pad Translator loose any swappability info of the components. It generate always 1 gate containing all the pins. Also all the pins are NOT swappable. the same appens from the translation from ALTIUM. Is there a way to receive the correct device.dev. ???? Also when i try to translate the PADS Library the translator loose all the Gate definitions inside the filename.p Any suggest?
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Forum Post: RE: Can't generate netlist in orcad capture CIS
Problem solved! I was dumb >< and thank you redwire :3
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Forum Post: Verilog-A to access wire bus of DUT
I am trying to create a verilog-A model to extract bus of nets of my DUT in a similar manner to the component deepprobe from analogLib in a Spectre transient simulation. These buses are at least 20-bit wide and it will be error-prone if I were to add them manually. I created a verilog-A block where I instantiate on the same level as my DUT and the code for the verilog-A is included below. If I try to use Cadence's verilogA editor,for the code below, I get the error "(TE-4309): extract failed for cellview "sandbox simCell_NetnameAccess veriloga". If I comment out the line " V(NetOfInterest01) From verilog-A level, string name is IDUT.UCOMP_TOP.INT_CLK is there something I need to do to process string to capture the triangular brackets? thanks! ========== verilog-A code ========== `include "constants.h" `include "discipline.h" module simCell_NetnameAccess(NetOfInterest01,NetOfInterest02); output NetOfInterest01,NetOfInterest02; electrical NetOfInterest01,NetOfInterest02; //parameter definition parameter string NetName = "DUT.XYZ"; string NetNameInt = "IDUT.UCOMP_TOP.INT_CLK "; analog begin @(initial_step) begin $strobe("From testbench level, string name is %s\n", NetName); $strobe("From verilog-A level, string name is %s\n", NetNameInt); end // END of [ @(initial_step) ] V(NetOfInterest01) <+ 1.0*V(NetNameInt); V(NetOfInterest02) <+ 1.0*V(NetName); end // END of [ analog ] endmodule
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Forum Post: Page Order in Hierarchical Design DE-CIS 17.2
Is there an automated method (not manual) for controlling the page ordering in a schematic design with a complex hierarchy? Manual editing will only cause problems as pages are added and deleted. For instance a schematic may have individual DRAM channels (A,B...) connected to multiple DIMMs which are located in hierarchical blocks. For each DRAM channel all connection to the hierarchical blocks are contained within a single page of the root schematic. The next page of root contains a different channel with different DIMMs. Currently the annotator appears to process all pages in the root schematic before processing the various hierarchical blocks which then appear in random orders once annotated. As an example, Channel A may be first in the root schematic but the DIMMs that are connected to channel A appear after the DIMMs for channel B once annotated (see below) page 1 Channel A page 2 Channel B page 3 Channel A DIMM 2 page 4 Channel B DIMM 1 page 5 Channel A DIMM 1 page 6 Channel B DIMM 2 It would be optimal for readability if the ordering could be controlled. In this example having the various DIMM pages be in sequential order directly after the page in which they are referenced by the hierarchical block seems to make the most sense (see below). page 1 Channel A page 2 Channel A DIMM 1 page 3 Channel A DIMM 2 page 4 Channel B page 5 Channel B DIMM 1 page 6 Channel B DIMM 2
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Forum Post: ModGen and Common Centroid Layout
Hello, I am trying to use ModGen to do Common Centroid Layout in CMOS using ModGen and Contraint Manager. Is there a tutorial/RAK about this ? I am getting some errors and wondering if they are kit related. The errors are mostly about symmetry - and Cadence complains the structure it has synthesized is not symmetric. In any case, thank you.
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Forum Post: get list of cells under specified Category which has recursive subcategories.
Hi, I am new to the community.cadence.com, Please help me to get solution for below query, Can we get list of cells under specified Category - MOSFETS (which has again a subcategory branches, like CMOS, DEMOS..etc)of a library. And I tried with ddCatFindCat, ddCatGetCatMemers commands, but failed to get cells if MOSFETS has many inner recursive subcategories. Thanks and regards, Basavaraj Tambur
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Forum Post: irun is not recognizing .scs files
I am running ams irun simulator Cadence IC6.1.6-64b.500.2 I get the following error: irun: *E,FMUK: The type of the file (./spiceModels.scs) could not be determined. irun: *E,FMUK: The type of the file (./amsControlSpectre.scs) could not be determined. The contents of the two files look quite normal to me. Here are the contents of amsControlSpectre.scs // This is the Cadence AMS Designer(R) analog simulation control file. // It specifies the options and analyses for the Spectre analog solver. simulator lang=spectre simulatorOptions options temp=27 tnom=27 scale=1.0 scalem=1.0 \ reltol=100e-6 vabstol=1e-6 iabstol=1e-12 homotopy=all limit=delta \ gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 digits=5 pivrel=1e-3 \ checklimitdest=psf tran tran stop=1u save=none write="spectre.ic" writefinal="spectre.fc" \ annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile Running with spectre alone works fine. I checked irun documentation but don't see where I can define extensions for spectre files, just veriog/systemVerilog/etc. files.
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Forum Post: RE: irun is not recognizing .scs files
Hi Eric, It looks to me that you are using a very very old incisive version where irun does not support .scs file. You can find the irun version you are using either at the top of the irun.log or if you do 'irun -version' in the UNIX terminal. The .scs files are supported in IUS 9.2 (which is also a very old version) & onwards. So if that's the case (an old version is being used) please move to a latest one. The latest incsive version is INCISIVE 15.1 Regards, Dimitra
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Forum Post: RE: Editing Signal names in ViVA
Hi Dimitra, I have old version, so tried with command given here. Its working well. Thank you so much Regards, Vijay
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Forum Post: RE: ModGen and Common Centroid Layout
Hi, Not sure how you do Common Centroid on your Modgen. You can use the "Common Centroid" Pattern Preset which is available in the Grid Pattern Editor Assistant in the Modgen Editor. There is this RAK Modgen on Canvas available which you can use as example. Hope it helps. Regards, Dimitra
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Forum Post: Changing x-value of a signal and/or handle signals with multiple outputs
Hello, My question from https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/38589/image-rejection-of-iq-mixer is still up :( So far I found the following hack: PSS+PAC, relative harmonic=1 and frequency sweep -100M ... 100M (for example). Then: leafValue(v("/vodi" ?result "pac") "harmonic" -1) + (sqrt(-1) * leafValue(v("/vodq" ?result "pac") "harmonic" -1)) Similarly as combining the I/Q data in time domain I add them in frequency domain (pac data) as complex value. The problem is that this maps both the positive and negative frequencies to the same (positive) frequency values. Question 1: When I plot this (or export to CSV/Table) one x value (e.g. 10 MHz) has 2 y values (one for positive and one for the negative frequency). How do I obtain the individual values? If I use value it just gives me the mean! Question 2: Is there any way to modify the x-value of the pac data to include negative frequencies? Thanks!
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Forum Post: RE: Verilog-A to access wire bus of DUT
Hi, I don't think that the extract fails because of the bus syntax. I think the failure happens because OOMR nodes can only be constant or parameterized. From the Verilog-A Language reference, it looks like you can not use string variable. Cadence Verilog-A Language Reference -- 9 - Out-Of-Module Reference So you will need to replace ' string NetNameInt = "IDUT.UCOMP_TOP.INT_CLK "; ' with ' parameter string NetNameInt = "IDUT.UCOMP_TOP.INT_CLK "; ' - you can also use localparam. Or you can use the literal string directly in the branch contribution statement, ' V(NetOfInterest01) "); '. Regards, Dimitra
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Forum Post: (Cadence Genus Synthesis) How to use more than one library file for synthesis?
Below is my Genus synthesis script.tcl, #Script #Setting Library and Design Path set_attribute lib_search_path ../lib/ set_attribute hdl_search_path ../design_files/ #Setting Library and Design Files set_attribute library tech1.lib #Analyze and Elaborate the Design File read_hdl -sv count.sv elaborate # Apply Constraints and generate clocks read_sdc ../constraints/constraints.sdc # Synthesize the design to the target library synthesize -to_mapped -effort medium # Write out the reports report timing > count_timing.rep report gates > count_cell.rep report power > count_power.rep # Write out the structural Verilog and sdc files write_hdl > count_netlist.v write_sdc > count_sdc.sdc How to write a script to import multiple library files say, tech1.lib, tech2.lib,... and synthesize the design with each and everone of them and generate reports? Also is there an option to make the tool to report best library to match timings of the design. Thanks.
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