Hello, I am trying to build a hierarchical design using Innovus, but I have a problem with closing the timing. My design is composed by different clone and master blocks. I partition the design and I do the block level implementation for each master partition. From the block level implementation I generate DEF, LIB and LEF files, along with the netlist (.v file) of each master partition. I manage to fix the timing in each partition. The problem comes when I am trying to close the timing on the top level. I am using the LIB and LEF files to create the layout and do the clock tree synthesis and Routing. Up to the point before I assemble the design everything looks to be ok. After I assemble the design the timing breaks down. One issue that I notice, is that the clock used after assembling the design, when I do the timing analysis, is the ideal clock. I use the update_clock_latencies command to get the actual clock and that is when the timing gets violated. I have also used the set_propagate_clock command in my constraints when importing the top design. That solved the ideal clock problem (now i am getting propagated clock), but the overall timing violation issue remained. Meaning that before assembling the design everything works as expected and the timing is met. After I assemble the design the timing gets violated. I am sorry if the question is kind of stupid, my experience is limited. Any help would be greatly appreciated. Best Regards, Dimitrios
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Forum Post: Hierarchical Design using characterized blocks timing issues
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Forum Post: IMC Coverage figures in ascii report differs from GUI & html report
Hi all, I have problems to get the same coverage figures shown in the GUI & html report versus the plain ascii report for a toplevel module. I am using the following script: merge -overwrite -message 1 -out cov_merge -runfile cov_merge.lst -metrics all load cov_work/scope/cov_merge load -refinement coverage/tja1448a/tja1448a_refine.vRefine report -overwrite -summary -inst -all -html -out cov_reports/html report -summary -inst ivn_smos10hv_tja14yx_tb.APP.PKG.DIE.u0_ivn_smos10hv_tja14yx_kookaburra -all -out cov_reports/tjf1441a_toplevel.rpt After execution of the refinement file as well in the GUI or checking after batch mode execution, the figures for the specific module in question are the same which is expected.However the same figures reported in the text file (last cmd of script) delivers a lower result for the Overall Average, Overall Covered, Code Average & Code covered and for these 4 categories the number is the same. See snapshot: Reporting_coverage.pdf Question: Why is the lowest figure printed for all 4 categories while in the GUI these figures are different? I used all kind of metrics options in the 2nd report cmd but still get the (lowest?) figure which seems to be related to the Expression categorie. Also using the 1rst report cmd and replacing -html by -text still yields in the same low figure of 67.29% IMC release: IMC(64) 15.20-s029 community.cadence.com/.../Reporting_5F00_coverage.pdf
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Forum Post: RE: get list of cells under specified Category which has recursive subcategories.
Hi Basavaraj, Can you please share your code and explain a bit more your example? I don't understand how your subcategories are structured by saying recursive subcategories. You cannot have a (sub)category which includes itself. Regards, Dimitra
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Forum Post: RE: irun is not recognizing .scs files
Thank you. This was extremely helpful. It turns out that there was an old INCISIVE version buried in the directory structure, and it was included in my $PATH. Fixing the path to only include the new INCISIVE version fixed the problem.
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Forum Post: How can you move/stretch schematic wires WITHOUT Virtuoso rerouting everything and making a mess?
I did try searching for this answer, but got lost in the zillions of search results so I thought I'd try here... I have a schematic that I've carefully and neatly laid out. If I edit it to do things like move instances or select regions of wires to stretch (all with wire rubber-banding in play) then Virtuoso steps in after I unclick my mouse and pretty much destroys my schematic layout with it's subsequent auto-routing. I realize some of this is to prevent errors like different wires landing on top of each other etc., however I've spent way, way more time cleaning up after some truly visually disgusting autoroutes that I'd rather always live with the danger of any errors I might create during my moving and stretching. Is there a way to configure Virtuoso to just take all the vertices and instances contained in my selection rectangle and yield straight line point to point wiring after I've done my edit? Bonus points if there's an optional way to constrain the movement of the selected set to be only in the X or Y direction. Thanks.
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Forum Post: RE: How can you move/stretch schematic wires WITHOUT Virtuoso rerouting everything and making a mess?
Groan - after looking around for this answer for quite a while, it just now fell into my lap. It's an embarrassingly obvious answer, so let me beat everybody to it and be the first one to call myself a dope. Once you start stretching your selected set, hit F3 and uncheck all the options for rerouting wires.
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Forum Post: RE: Importing PADS footprint into Allegro 17.2
Is there a way to do this without PADS? Like say if I only have Allegro?
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Forum Post: How Allegro is calculating Via delay (Z-axis delay) from propagation velocity factor
Hello Group, I really had a hard time to identify formula through which Allegro is calculating via delay (z-axis delay) from propagation velocity factor. In CM, default value for propagation velocity factor is set as 1.524 e +008 = 1.52400000000 while in cross section, I used FR-4 with 4.5 di-electric constant (default values for FR-4 from Cadence database) In Allegro, via length is 1000 mil. From ECS, via delay came out to be as 0.16667 ns (I already subtracted trace delay from total delay of trace & via). However for 1000 mil trace length, it shows delay as 0.1738 ns I have below questions. 1) How this value 0.16667 ns (via delay) is calculated based on 1 inch via length with factor 1.524 e +008 ? As per pdf documentation, this velocity factor is used to convert units (from length to time) but not sure how. 2) Why delay is different between 1 inch via length and 1 inch trace length? 3) Can I say that via delay does not depends on Allegro cross section settings, rather just on propagation velocity factor? 4) Do we need to change this propagation velocity factor based on dielectric material in cross section? Sorry for many questions and appreciate if some one could shed light on the same.
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Forum Post: RE: Importing PADS footprint into Allegro 17.2
Hi dgrolnu, you need to extract the *.p and *.d files from pads. Is not possible in Allegro (also OrCAD PCB) to extract them from original pads libraries *.ld9, *.ln9, *.pd9, *.pt9 files. At the moment the translator work in this mode only. Best regards, Gianni.
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Forum Post: RE: Importing PADS footprint into Allegro 17.2
Hi dgrolnu, you need to extract the *.p and *.d files from pads. Is not possible in Allegro (also OrCAD PCB) to extract them from original pads libraries *.ld9, *.ln9, *.pd9, *.pt9 files. At the moment the translator work in this mode only. Best regards, Gianni.
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Forum Post: RE: Importing PADS footprint into Allegro 17.2
i have noted another error. the translator routine use for the internal pads definition for all internal layers NOT the definition of the internal pad of PADS, but the diameter of the antipad pad of the second layer. so all the internal pads diameters are wrong.
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Forum Post: Possibility to open Cases and how to ask improvements on PCB designer
Hi, i need to know how to open Cases (because when i login inside the Support i dont have the button to open new cases, but strangely i can see the possibility to see my cases already sended.!!!!!???????). Also i need to know how is possible send enhancements request for new features. any reply will be appreciated.
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Forum Post: Possibility to open Cases and how to ask improvements on PCB designer
Hi, i need to know how to open Cases (because when i login inside the Support i dont have the button to open new cases, but strangely i can see the possibility to see my cases already sended.!!!!!???????). Also i need to know how it is possible send enhancements request for new features. any reply will be appreciated.
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Forum Post: RE: Possibility to open Cases and how to ask improvements on PCB designer
Submitting a new case: Go to support.cadence.com, in the top menu bar, hover over "Cases" and select "Submit Case" If those options are not available, then my guess is that your host ID entered is not correct.
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Forum Post: Dangling wires/extra net length using -sroute command
Hello, I am using multiple power domains in my design and while doing the routing of power structures (using the -sroute command), I see that the VDD_CORE1 wire (in my case) always extends by a small margin beyond the power domain. Before running the sroute command, I use the modifyPowerDomainAttr commad to adjust the size of the power domain so that it sits exactly on top of the power rail I want to route. And then I use the sroute command. But I keep getting this "dangling" wires which is leading to further DRC errors; also sometimes for the global PWR rails, the routing is incomplete leaving the nets unconnected. Please assist me in this. I am attaching a screenshot of the issue and the command I am using. modifyPowerDomainAttr PD_1 -box 188 238 262 312 -minGaps {4 4 4 4} // adjustPower domain to accommodate the VDD_CORE1 rail exactly sroute -connect { blockPin padPin padRing corePin floatingStripe } -layerChangeRange { M1(1) LB(9) } -blockPinTarget { nearestTarget } -corePinTarget { firstAfterRowEnd } -allowJogging 1 -powerDomains { PD_1 } -crossoverViaLayerRange { M1(1) LB(9) } -nets { GND } -allowLayerChange 1 -targetViaLayerRange { M1(1) LB(9) } modifyPowerDomainAttr PD_1 -box 200 250 250 300 -minGaps {4 4 4 4} // re-adjust back to original Thanks, Kashif
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Forum Post: File Type Clarity - Using Built-in Capture Symbol Models to Create Non-Associated Custom Parts and Software Version Capabilities
What I'm trying to do... I need to simulate two NMOS transistors each with custom parameters. I would like to have my own Library in which I can build individual non-associated (meaning: if I change the modal name and parameters for one it only applies to that model), custom parts that have functionality and can be used in the same schematic. I've been trying for two days now and have read many articles, but still I don't clearly understand what's going on with all the different file types and there functionality in the different programs (ie: lite/student versions of Pspice, Capture, Pspice-Model editor). What I've tried to do so far... In Capture I add a part to the screen. Then, I select, right click the part and "Edit Pspice Model".. Then, in Model Editor I try to change the Model Name and a one off "part" the that will be the same king of device in my Schematics but with different parameters and a different model name. I've also tried to open Model Editor on it's own and make a library and add parts but it doesn't recognize the .OLB Breakout files. What I don't Know... I don't know what the difference is between the file types (.LIB .OLB .MOD .OBJ) and I don't understand the association in models and libraries and (you name it). I understand that there maybe can also be different models based on locality, meaning simulation profile specific vs global library vs Schematic and such. RESTATED. I just want individual N-Channel MOSFETs on the same schematic in Capture, Whose properties can be different (ie LAMBDA, VTO, W, L, ETC.) AND Whose names can be different. Thank you in advance, to anyone that can help.
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Forum Post: RE: File Type Clarity - Using Built-in Capture Symbol Models to Create Non-Associated Custom Parts and Software Version Capabilities
Also I'd like to use the 4 terminal device as well, and this seems to be maybe unavailable to make your own custom variant?
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Forum Post: RE: PSS not completing in post extraction design
Hi! I realized that PSS uses RAM to store data. When I ran the analysis on a machine with 256 GB RAM the analysis completed. However, it used up 242 GB of memory and thus there is no memory left for pnoise analysis. Any way in which I can point pss or pnoise to use disk space instead of RAM? Thanks!
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Forum Post: IC617 import GDS file from TSMC.
Hi, Can I ask a favor? I am trying to import an io pad lib from TSMC into Cadence IC 617. This is how I tried to do it. I firstly create a library , name it io_pad and attach it to my TSMC PDK library (tsmcN65). Then in the CIW, file----import----stream then choose Stream file: home/..../xxxxxx.gds Library: io_pad then click translate. There are 0 error and 3 warnings. WARNING (XSTRM-75): Target library 'digital_cell' is attached to the technology library 'tsmcN65'. Therefore, the technology file is opened in read-only mode. All the undefined layer-purpose pairs will be dropped. WARNING (XSTRM-107): Existing cells in the target library will be overwritten if the cell names in the Stream file and the target library are the same. To prevent this, set the '-writeMode' option to 'noOverwrite'. WARNING (XSTRM-363): The technology library has been modified during XStream In translation. Cannot save the changes in the technology file because it is open in read-only mode. Though I can see the io pad layout in the library, can anyone tell me what caused these warnings? Does these warnings matter? Thanks
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Forum Post: Cadence simulation setup－core usage-
Hi team I have posted this question on other EE forums and received conflicted answers. But I think no where can give me a better answer then here. So here we go Now I am using CADENCE IC 617 and MMSIM151 on a Linux machine with 10 cores CPU (20 threads). The simulation setup is like this: ADE L --> Setup --> High-Performance Simulation Options. Then I click APS. choose Error Preset: DO not override; Use ++aps; Multi_Threading Manual #Threads: 19 (1-19) But when I try to simulate, the total CPU usage is about 16% and a lot of cores are idle. The total simulation time-steps are 2210000 steps (transient time is 2210ns and simulation step is 0.001ns. ) this cost me more than 2 hours per simulation. this is the info [xxxxx@xxxxxx ~]$ top top - 00:55:30 up 4 days, 2:38, 6 users, load average: 2.00, 1.61, 1.57 Tasks: 422 total, 2 running, 419 sleeping, 0 stopped, 1 zombie %Cpu(s): 10.1 us, 0.7 sy, 0.0 ni, 89.2 id, 0.0 wa, 0.0 hi, 0.0 si, 0.0 st KiB Mem : 65727816 total, 538404 free, 3730288 used, 61459124 buff/cache KiB Swap: 32964604 total, 31957960 free, 1006644 used. 61534544 avail Mem PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND 7718 xxxxxxxxxxxx 20 0 1744388 469288 4152 R 206.6 0.7 1460:39 spectre It seems the CPU is very underused. My questions are: 1. Does anyone know how I can setup the software to use all or most of the CPU power to speed up the simulation? 2. What dictate the time step of the simulation? Thank you very much Allen
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