You cannot import DXF directly into Capture schematic. You can import/pace picture formats (.bmp, jpg etc)
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Forum Post: RE: Import DXF in Orcad Capture CiS
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Forum Post: Innovus CTS for a range of clock
Lets assume, I have a clock source whose frequency can very within a range (like within 6MHz to 9MHz range).I have a verilog circuit module where I would like to use this clock. How can I configure Innovus to perform clock tree synthesis and post route synthesis so that this total circuit will not be susceptible to any clock related violation (setup time, hold time etc.) within a particular frequency range? What kind of possible setup should I use ? thank you for your time.
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Forum Post: RE: pp output of `case' expression in procedure definition changes after the procedure is run
Tom, The problem is that case() doesn't support comparison of a list as the matching value because it would then be ambiguous potentially with the situation where the target branches have a list of alternatives. Clearly it partly works - but it is not documented as working this way; the documentation says that the value compared should be a scalar value. As you can see, the pretty printer doesn't know about this usage and mangles it when decompiling. So I would advise using cond instead, or writing your own macro that looks like case, but expands into cond. Regards, Andrew.
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Forum Post: RE: How to continue execute a skill script after a form popup in layout ?
Max, Tom, hiEnqueueCmd is effectively the same as hiRegTimer with 0 as the time (sort of). What it does is insert a command into the queue of SKILL commands to be executed when the UI responds; it's similar to the fact that you might have a blocking function (which doesn't return until the form has been OK'd for example) but yet you can still type SKILL functions in the CIW. It is not dependent upon self_align returning. Tom, hiRegTimer is still useful if you want to schedule something some time in the future (i.e. a non-0 number of 10ths of a second in the future). Also, if my memory is correct, hiRegTimer existed for a very long time but hiEnqueueCmd is relatively recent (I'm sure even that has been around for a long time though). So I tend to use it for its semantic benefits - it more clearly signals the intent when you read it in code. Regards, Andrew.
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Forum Post: RE: Modeling and simulation of FinFET in cadence
have you find the solution
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Forum Post: RE: Changing x-value of a signal and/or handle signals with multiple outputs
Quick answer - which may solve both questions (I don't have time post-vacation to do an experiment to check what you're saying as I have a lot of catching up to do!). On the pac options form, set the freqaxis parameter to "out" (rather than the default "absout"). Then you should get the negative frequencies in the data. Regards, Andrew.
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Forum Post: RE: Image Rejection of IQ mixer
Normally you'd use pxf to investigate image rejection in a downconversion mixer. You can specify the output frequency range in the pxf sweep and then you can plot the transfer function from different sidebands of each source to the output. Not sure whether it's what you want in this case, but that's how I'd normally do it rather than using pac. Regards, Andrew
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Forum Post: QRC Lvs Extracted View
I am using QRC with LVS Extracted View output in order to generate the circuit netlist from the layout. The netlist (created with ADE-L) is the reported below. However I would like to add a custom extra line in a given subckt section (i.e I0 (net1 net2) myblock) to include an additional parasitic model for my MEMS simulation. Is there a method for adding such a line in a spectre netlist (i.e. nlPrintComment netlister ....)? Thanks, Pietro // Library name: test // Cell name: diode_Test_Top // View name: av_extracted // Inherited view list: spectre cmos_sch schematic veriloga ahdl subckt diode_Test_Top D G S Sub avD218_3 (NW2 I1\|net11) iprobe avD218_2 (NW1 I1\|net11) iprobe avD218_1 (SUBSUB Sub) iprobe TO ADD: I0 (net1 net2) myblock \#7cI1\|avD201_5 (Sub I1\|net11) nwdiode area=2.35472e-10 \ perimeter=0.00012938 dbv=0.0 m=1 \#7cI1\|avD201_4 (Sub I1\|net11) nwdiode area=6.4e-11 perimeter=3.2e-05 \ dbv=0.0 m=1 .... .... ends diode_Test_Top // End of subcircuit definition.
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Forum Post: RE: using auto-vias through SKILL
Since you're already interacting with customer support on this, I'll let them comment rather than duplicating work (plus I'd have to research the details of what has been done via the support case that you didn't provide the number for). Regards, Andrew.
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Forum Post: RE: Is there a way to describe the charge across the device as a function of voltage?
It would help if you provided the complete code rather than just a two line snippet. Given that the ddt function is used in countless models (and it's a pretty vital part of VerilogA modelling), it's unlikely to be a general problem but a specific issue with how you're using (it could be a bug with the specific usage, or it could be a bug in your model). Regards, Andrew.
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Forum Post: RE: spectre solver for veriloga
Yuanqi, We'd have to see the example to understand what's going on - my suggestion of breakpoints was only a guess, so it's likely to be something more subtle than that. The point of using breakpoints on a large PWL file is to improve the accuracy of the simulation, not to make it faster. Clearly that's not happening in this case - so it must be something else. Best to contact customer support as I mentioned earlier (no need to wait for one of the team to visit you - this is what customer support is for!) Regards, Andrew.
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Forum Post: RE: [URI] RelXpert support for HISIM_HV model cards.
Fabio, I suggest you raise this with customer support - it's going to to be hard to debug without more details of precisely what you're doing. Also, if it works with spectre native, there's not a huge reason to use RelXpert; the native mode is intended really to be a more direct way of running reliability analysis than the older RelXpert flow. Kind Regards, Andrew.
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Forum Post: RE: Verilog A ADC design
I selected the 10 signals d0 to d9 and then did (in the ViVA graph) Measurements->Analog to Digital. I specified the mid-value for the threshold, and made sure that the "Make Bus" was checked. If the bits are in the wrong order (MSB->LSB) then you can fix this by clicking on the Signal/Expr Names column heading to reverse the sort. You can control the radix and give a name for the bus - and then it adds the bus to the output. Hopefully that's clear enough without me posting a picture of the form. Regards, Andrew.
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Forum Post: RE: How to continue execute a skill script after a form popup in layout ?
Thanks, Andrew! That's great !!!! Gong
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Forum Post: RE: QRC Lvs Extracted View
Hi Pietro I think you can do it as follows: a. Create a cell named "myBlock". It should have a symbol and spectre view b. Add the symbol view of the cell to the extracted view c. Select the newly created instance d. Go to "Connectivity->Nets->Propagate" and add the appropriate net names for each terminal of myBlock e. Execute the following cmds in CIW: cv=geGetWindowCellView() dbSetConnCurrent(cv) dbSave(cv) f. Netlist the extracted view. It should now include myBlock instance Best regards Quek
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Forum Post: RE: QRC Lvs Extracted View
Hi Quek, thank you for your reply. Is it possible to do these operations with a SKILL script? Or by modifing the way the netlist is created? Best Regards, Pietro
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Forum Post: RE: File Type Clarity - Using Built-in Capture Symbol Models to Create Non-Associated Custom Parts and Software Version Capabilities
There are two libraries in use, the graphical library for Capture, an OLB file containing the parts that are placed in the schematic, and the model simulation library used by the simulator, a LIB file containing "plain" text (for the most part) describing the model. The graphical library and the simulation library are linked by two properties attached to the schematic part, the Implementation - name of the model in the Model library, and the PSpiceTemplate - used to map the Pin Names on the schematic part to the Nodes in the simulation model. IF you place a part from the breakout library, you can use Edit PSpice Model from the pop-up with the part selected, this will create a local library specific to the design with a copy of the default breakout part that can then have the parameters modified and the name of the model changed within the Model Editor. Without a license, the Model Editor only supports creating new Diode models from scratch.
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Forum Post: RE: QRC Lvs Extracted View
Hi Pietro I think modifying the extracted view is most probably easier than manipulating the netlister. : ) Would you please try the following? procedure( CCSaddInstToExtractedView(lib cell view libM cellM viewM net1 net2 term1 term2) let( (cv cvm pt inst netId termId) cv=dbOpenCellViewByType(lib cell view "" "a") cvm=dbOpenCellViewByType(libM cellM viewM) pt=leftEdge(cv~>bBox):bottomEdge(cv~>bBox)-1 inst=dbCreateInst(cv cvm nil pt "R0") foreach( (net term) list(net1 net2) list(term1 term2) netId=dbMakeNet(cv net) termId=dbFindTermByName(inst~>master term) dbCreateInstTerm(netId inst termId) ) ;foreach dbSetConnCurrent(cv) dbSave(cv) dbClose(cv) dbClose(cvm) ) ;let ) ;procedure E.g. CCSaddInstToExtractedView("A_testcase" "inv1" "av_extracted" "gpdk045" "resm1" "symbol" "aaa" "bbb" "PLUS" "MINUS") The above cmd will add an instance of resm1 into the av_extracted view. Nets aaa and bbb will be assigned to terminals PLUS and MINUS on resm1. Best regards Quek
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Forum Post: PQ and EFD 'family name' in MAGNETIC PART EDITOR
Hello, To Create PQ and EFD family type transformer in magnetic part editor? Is there any way in data entry to provide PQ and EFD Family As well? regards, jishu
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Forum Post: RE: Import DXF in Orcad Capture CiS
OK. Thanks
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