Hi Saloni, To continue debugging, I placed a symlink of cds.lib at the vfi batch run directory. I then get some issues with the QRC runDIr. If I specify the QRC path up to RCC_SPICE, it looks for _qrc_tech_dir, if I specify up to RCC_SPICE/tmp/ it looks for _save_layers, and finally, If specified RCC_SPICE/tmp/ , then it says failed to start QRC module 'shapeServer'. Do you know what is missing? We only get these errors running in batch mode. Test run 1, using the following line in emir.conf: emirutil qrc_output=[runDir= / / /EXT_QRC/RCC_SPICE/ runName= ] Error: Failed to open / / /EXT_QRC/RCC_SPICE//_qrc_tech_dir Test run 2 (I found _qrc_tech_dir in tmp/ so I added that to the path and rerun) emirutil qrc_output=[runDir= / / /EXT_QRC/RCC_SPICE/tmp/ runName= ] Error: Failed to open / / /EXT_QRC/RCC_SPICE/tmp//_save_layers Test run 3 (I found _save_layers in CTLE_Core so I added that to the path and rerun) emirutil qrc_output=[runDir= / / /EXT_QRC/RCC_SPICE/tmp/ runName= ] Failed to start QRC module 'shapeServer'. Please check QRC installation or contact Cadence Customer Support. Regards, Henry
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Forum Post: RE: Voltus-FI: How to automate the creation of selfheating-aware EM/IR text reports after every run
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Forum Post: RE: Simulation is too slow
The advantage of @(cross) is that it causes the simulator to take a timestep at (or rather very near) the crossing point; without this, the model would only be evaluated wherever there already is a timestep placed by the simulator, and so you won't have much control over where the decision to go high or low is. The discontinuity in the output can cause a challenge with convergence, which is why I also recommended transition. However, it's really hard to see what's wrong without being able to see the circuit and the other models. You may have ended up with a feedback loop which causes the timestep to collapse. The circuit doesn't look large, so I'm guessing the problem is fairly simple - but it would be pure guesswork to figure it out without any real data. I suggest you find a way to report this to customer support though your university program. That way somebody may be able to take a look at your testcase. Regards, Andrew.
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Forum Post: RE: Plot large signal conversion ratio of a simple dc-dc converter
You might be able to use the information in my app note . That talks about simulating DC to DC converters using SpectreRF - and maybe you could sweep the duty cycle. Regards, Andrew
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Forum Post: RE: Plot large signal conversion ratio of a simple dc-dc converter
Thank you very much, Andrew. Reading that app note, I am still not sure if PSS can be used to plot the conversion ratio with duty cycle as the picture above. I tried another method that set duty as a variable and then run parametric the duty variable in transient analysis and plot conversion ratio M = Vout/Vin. With this I got a set of curves Vout/Vin with time for different duty cycle. However, there are some problems. First, I only want to calculate conversion ratio M = Vout/Vin at steady state and transient period. Second, I would like to plot duty cycle as X axis not time. Could you give me some advice?
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Forum Post: RE: Bottom soldermask Gerber Problem
No workaround needed... there is something wrong in your artwork setup. Post a screenshot of the artwork setup or post a zip of the board.
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Forum Post: RE: Bar over pin name
That is an OrCAD feature only. In Concept you have to draw the bar
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Forum Post: RE: To get resistance of track
That's why they sell the upgraded license to avoid all the nonsense if you don't have it. Otherwise use some freeware tools on the side to calc or use Excel.
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Forum Post: terminals "cannot be found in the switched master of the instance"
I get the message in the title when I try to simulate my circuit. The circuit contains a symbol of a custom device which I described in Verilog-A code. I know the Verilog-A code should work because I just copy/pasted it from a code which has worked in the past. How can I resolve this issue? Below is the full error message.
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Forum Post: RE: Trace length matching
add a default signal model to the resistor and then Allegro with auto create an xnet of the two nets either side of the resistor (one net combined). Watch https://www.youtube.com/watch?v=KLPfatmaxz0&t=13s
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Forum Post: RE: Voltus-FI: How to automate the creation of selfheating-aware EM/IR text reports after every run
Hi Henry, Can you set the below env var before launching your Spectre run: setenv CDS_MMSIM_VOLTUSFI_ROOT $CDSHOME This will call the report generation utility 'emirrerpot' from IC installation instead of Spectre. As text reports generate ok from Voltus-Fi console, let's use the same version in batch-mode too. Some more information here: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000007MgvlUAC&pageName=ArticleContent&sq=005d0000001T4VEAA0_20185191636205 Test run 3 appears to be correct if you don't get errors for missing files; it's hard for me to guess the name for runDir and runName without looking at Quantus command file. If in doubt, you can get the settings from Voltus-Fi GUI because you would have entered runName and runDir under QRC Run field. Regards, Saloni
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Forum Post: RE: Voltus-FI: How to automate the creation of selfheating-aware EM/IR text reports after every run
Also, can you tell me your ICADV version? The support for reading 'emirutil cds.lib=' was introduced in ICADV12.3 ISR14 I think, so once you set CDS_MMSIM_VOLTUSFI_ROOT and are using a later version, you shouldn't have to create a soft-link to cds.lib.
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Forum Post: RE: terminals "cannot be found in the switched master of the instance"
To debug this, would need to see several things: The top of the veriloga module - showing the module line and the port definitions What the switch view list is (or config) - i.e. which view is being switched into It appears to me that the "veriloga.cdb" file in the test_func11/veriloga cellView hasn't got any record of the p and n terminal - so maybe you saved and exited the editor when there were errors in the VerilogA? Can you open the veriloga view, add a blank line, save and exit the editor - see if you get any parser messages and see if that resolves it. I could get you to run some SKILL to take a look at the database, but it seems a bit pointless given that it's clearly wrong. My guess is that the veriloga code has been edited outside of icfb, but who knows? You'll have to remind me which version of spectre you're using (I can see from the image dump that it's IC5141 for icfb though just from the graphics). I can't remember the versions used by every user on the forums, unfortunately (which is why the forum guidelines ask you to provide this information). Kind Regards, Andrew.
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Forum Post: RE: Virtuoso, monte carlo simulation to measure fervency of ring oscillator
Hi Andrew I need to measure the frequency of ring oscillator in dc sweep simulation ( frequency vs vol) thanks
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Forum Post: RE: Bottom soldermask Gerber Problem
Thanks for the reply. See below for the screenshot of my bottom soldermask artwork setup. See anything wrong?
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Forum Post: RE: Virtuoso, monte carlo simulation to measure fervency of ring oscillator
[quote userid="384390" url="~/cadence_technology_forums/f/custom-ic-skill/38682/virtuoso-monte-carlo-simulation-to-measure-fervency-of-ring-oscillator/1354861#1354861"][/quote] I need to measure the frequency of ring oscillator in dc sweep simulation ( frequency vs vol) Well, that's very simple. You can't. Since a DC analysis is not time-varying, your oscillator will not oscillate and hence there will be no frequency to measure. Andrew.
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Forum Post: Vref Opamp Simulation
Hi everyone, I am simulating inverse voltage using opamp with single Voltage. to not use negative input voltage. I use opamp model in adhLib. But circuit cannot cut negative input voltage. Can you explain for me how to fix this? Thank you.
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Forum Post: RE: Funckey and Alias in Env file work erratically in latest Hot Patch
Paul, My issues have gone away thanks to Hotfix 38. Yea!
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Forum Post: RE: Funckey and Alias in Env file work erratically in latest Hot Patch
Yes, they have fixed all of my issues. Seems faster too. Finally!!
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Forum Post: RE: Bottom soldermask Gerber Problem
You have a single sided design. Copper only on top based upon your description. Why are you outputting the bottom mask? The is no need for it. You are not soldering anything and the is no copper to cover. However, it is still interesting that your bottom mask artwork would not output correctly. Maybe it was due to the fact that there were no D Codes or anything to compute. So, it went bonkers. In these cases the output should warn the users that there is nothing to produce and will terminate. If you still would like to flood the bottom of your board with a mask anyway. I suggest you add note on your fabrication drawing telling the PCB supplier to flood the bottom with mask. They don't need an Gerber to do that.
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Forum Post: RE: Virtuoso, monte carlo simulation to measure fervency of ring oscillator
Hi Andrew I need to make PUF (Physical Uncolnable Function ) and test it using monte carlo analysis so, i need to measure the frequency of ring oscillator vs the temperature variations . Many thanks
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