I guess I didn't describe the board properly. I have a plane on the bottom side and some tented vias, but no features in the bottom soldermask. I attached the file that is generated. My gerber viewer doesn't recognize it, but when I open it in a text editor it seems to be ok. community.cadence.com/.../BOARD_5F00_SM_5F00_BOT.art
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Forum Post: RE: Bottom soldermask Gerber Problem
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Forum Post: Opening ModGen (Module Generator) in Cadence
I was working with ModGen two weeks ago and it was fine. Now, I wanted to go back and do some modifications but I cannot open the menu! I used the following path: Windows -> Assistant -> Constraint manager But now, I do not have such menu which seems quite weird. Here is the screenshot: Does anyone know what is the problem and how can I solve it? Briefly, I want to see the window on the right side of the Cadence to be able to edit ModGens and create new ones. Cadence Version is IC6.1.6-64b.500.6. Thanks.
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Forum Post: RE: Bottom soldermask Gerber Problem
Inside your Gerber file you are missing XY coordinates and a few other things. Compare it to an artwork file that works. You will see what I see. I did try to re-import your file back into the PCB editor. During import it stated "no photoplot file specified. Due I think to the missing stuff. Try just adding a shape fill to layer "Board geometry - Bottom Solder mask" over the entire bottom of your board and rerun your artwork.That should work for you. I just did the same thing to verify the results. Good Luck
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Forum Post: Running parallel processes in SKILL code
Hi, I am writing an oceanXL script to launch multiple runs in parallel. While I set each run with ocnxlRun( ?waitUntilDone nil) in the loop to set up the circuit, after all runs are defined and launched I then wait for the runs to end with ocnxlWaitUntilDone('All). In the mean time, there could be a lot of runs and potentially taking a few days to finish. I want to be able to monitor a few finished simulation results to determine whether I want to continue with all simulations. So here in the attached eample I inserted a block of code to look for the results directory. The problem is, the while loop seems to block the execution of the ocnxlRun's and will not produce any results until I exit the while loop. Obviously I can't put the monitor block after the ocnxlWaitUntilDone('All) command since it will wait for all to finish and defeat the purpose. My question is, can I launch a parallel process to monitor the progress of the simulations? Thanks in advance for any help. Ed
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Forum Post: RE: Opening ModGen (Module Generator) in Cadence
The constraint manager is only in Virtuoso Layout Suite XL (or GXL). You're using VLS L from the picture, and so the assistant won't show up. ModGens themselves require GXL licensing and so must be used in the XL or GXL environment. Regards, Andrew.
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Forum Post: RE: Virtuoso, monte carlo simulation to measure fervency of ring oscillator
Hi Amin, I assume you mean a Physically Unclonable Function (unless Uncolnable is some term I've never heard of) - not that this is terribly relevant to the question. I still don't understand why you think a DC sweep is suitable to measure the frequency of a ring oscillator. Normally you'd use either a transient simulation and then take the average frequency over a range of time after the oscillator has started, or better still use PSS oscillator mode and then use the expression on the direct plot form to find the frequency (this will find the steady state frequency). You could then run this in Monte Carlo in ADE XL, Explorer or Assembler, to get the variation of the frequency. If you want to see how that variation varies with temperature (and how the mean frequency varies with temperature), then you could sweep temperature as part of a corner (in ADE XL, Explorer or Assembler), or by sweeping the variable "temperature" in ADE Explorer or Assembler (in ADE XL you can't do a variable sweep at the same time as Monte Carlo, unless you do it within the corner definition). Please do read the forum guidelines . You'll find if you ask a well-formed question, in the right forum (I doubt you're really asking about the SKILL language), with enough information about what you're trying to do, what you've tried, and which tools and versions of the software you're using, then you're much more likely to get a focussed answer. Because you didn't provide any of this, anyone (including me) answering here has to guess what you really want... Regards, Andrew.
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Forum Post: RE: Vref Opamp Simulation
Your first step would be to ask a question that makes sense. I have no idea what you're asking (or why you're asking it in the SKILL forum). Kindest Regards, Andrew.
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Forum Post: RE: Opening ModGen (Module Generator) in Cadence
Thank you Andrew. Using the Layout GXL, the problem is solved and I am able to work with ModGen. Thanks again!
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Forum Post: RE: addStripe command for multiple power domains
try getting rid of the start/stop arguments.
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Forum Post: RE: Hierarchical Design using characterized blocks timing issues
Did you balance the clock tree to your blocks? I haven't done clock trees in a long time, but in the old CTS method, we would use a "macromodel" that basically told the top-level what the insertion delay inside the block was, so that the top-level tree could balance the leaf flops. Even with that though, you are likely to see some timing violations in flat timing that you did not see at the block-level. This is normal.
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Forum Post: RE: Dangling wires/extra net length using -sroute command
this seems strange - are the vertical stripes on grid?
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Forum Post: RE: Encounter's "common timing library"
what version are you using? the libraries should be set up using a MMMC file so that you can have as many analysis views as your design requires...
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Forum Post: RE: Funckey and Alias in Env file work erratically in latest Hot Patch
Well very cool Dale, That hot key issue was kind of interesting, I can honestly say I never had a problem with them in the prior cuts of 17.x. On a related note MS did push down an update a few months back that caused me some issues. Basically the mouse would go away for a short time.. During those periods I did notice that hot keys failed to work. It was almost like a quick glitch... Kind of wierd. Anyway, all seems good now. Yay !
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Forum Post: RE: Bottom soldermask Gerber Problem
Hi Your output does not contain any pcb items on the bottom soldermask layer from which a gerber gcode can be generated from. Basically there is no bottom solder-mask so the bottom surface of your board will be completely covered in mask that is assuming you want the bottom of your board covered in mask. You may want to consider including your board outline on that soldermask layer, (BoardGeometry - Outline) This way there will be some information available to see when your board house imports the gerber file. While it is not always necessary a good rule of thumb is to include the physical board outline layer on each photoplot you wish to create. all the best Paul
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Forum Post: Constraint region overrides net based constraints
Using 17.2 I have created a rigid-flex PCB. By default when a zone is created PCB Editor creates a constraint region around the perimeter of this zone. This is fine except when the nets within this zone require net based spacing requirements. PCB Editor seems to prioritize the constraint region over the net based constraints which ends up violating net spacing rules but no DRC is created. Is this normal? Is there a way of setting the priority of the spacing constraints? Thanks!
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Forum Post: How to set Vref of Opamp in adhLib
Hi everyone, I use Opamp in adhLib to simulate the inverting voltage circuit. with input Voltage is linear funtion in range -1 to 1 ( I use Vpwlf to make it) My point is with input Voltage in [-1;0], the ouput of opamp is zero. And with voltage in [0;1], the ouput is inverted to [0; -1]. So I use Single Supply Voltage. This is my circuit and results. Can you tell me why I cannot get my point? Thank you
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Forum Post: RE: Is there a way to describe the charge across the device as a function of voltage?
Thank you for your help Andrew. I'm well aware how to solve the discontinuity near the beginning. Could you explain what you mean by "numerical smoothing." This model is working pretty close to how I would want it to work but the current response still appears a bit jagged. Any other suggestions aside from transition/slew? Thank you
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Forum Post: RE: Dangling wires/extra net length using -sroute command
It's fixed....I had to decrease using the modifyPowerDomanAttr the length by about 0.12 um....so instead of say, 30 it fixed to 29.844 say... Thanks!!
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Forum Post: RE: addStripe command for multiple power domains
precisely...using both x and y components doesn't exactly help...use either of them....also using -minGaps {...} is better instead of -gapEdges
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Forum Post: RE: Encounter's "common timing library"
yes..this happens as your MMMC file overwrites it...so set up individual views for each instant...something like _MAX_TYP $LIB_PATH and if you have set_analysis_view enabled or update_delay_corner make sure it references each library...so for 3 cases you should have 3 views on delay/power etc... I would recommend something like create_library_set -name library_typ_device -timing [list $your_libraries_here] do this for max and min and other corners accordingly
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