Folks, Been having this issue since I installed Cadence SPB 17.2 (now at ISR 37). All products work fine EXCEPT Allegro Router or Specctra as it was originally known. Once opened up, you cannot quit unless you go to the the Windows 7 Task Manager and "end" the application. Here is the funny thing, I have VMware Workstation Pro installed with Windows 10 (64 bit) Pro installed and I can run any Cadence SPB 17.2 Allegro product within that environment and everything, including Specctra, work perfectly. No problems at all! Question: Does the Specctra product in version 17.2 have issues with either Windows 7 or could it be the Graphics card (Nividia K600 PCIe16 with 1 Gbyte RAM) cause this issue as when I am inside the VMware machine in Winodws 10, I am using the VMware video driver, not the Nividia software driver. Thoughts...especially from Old Mouldy! Thanks! Chris
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Forum Post: Cadence Specctra (Allegro Router) 17.2 Issues in Windows 7 Pro (64 bit)
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Forum Post: RE: Cadence Specctra (Allegro Router) 17.2 Issues in Windows 7 Pro (64 bit)
I have seen this behavior when you run the Allegro Router for the first time during an Allegro session, it will remain running in the background until you close the Allegro session even if you are not using it. I believe this was to allow quicker execution of the black box type of commands that call the Allegro Router. (i.e. Route > PCB Router > Route Net(s) by Pick) Is this what you are seeing? I wonder if there is a configuration on the VM that cleans up the suspended processes automatically.
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Forum Post: SKILL function for getting point ID (or netlist directory) in ADE XL
I am writing custom SKILL function to process certain file located inside of netlist directory, in IC6.1.7-64b. This file is generated by an internally developed tool of which source code I don't have access to. I am calling my custom function in ADE XL output expression. This function needs to read the file, process data, and show result for each simulation point in ADE XL result window. Let's say variables are defined as following. ssName=axlGetWindowSession() sdName=axlGetMainSetupDB(ssName) hstName=axlGetHistoryName(axlGetCurrentHistory(ssName)) hstEntry=axlGetHistoryEntry(sdName hstName) pCornerName=axlGetCornerNameForCurrentPointInRun() When I run axlGetPointNetlistDir(hstEntry "test") when my test name is "test", I will get something like this. "[some directory hierarchy]/adexl/results/data/Interactive.0/ psf/ test/netlist " However I need to know the netlist directory of each point where each file is saved. Desired result looks something like this. "[some directory hierarchy]/adexl/results/data/Interactive.0/ 1/ test/netlist " If I know point ID and run axlGetHistoryEntry(sdName hstName ?cornerName pCornerName ?designPointId [point ID value]) I will be able to get the netlist directory I want. Does anyone know if there is any function that returns point ID, or returns netlist directory of each simulation point? Thank you.
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Forum Post: RE: Verilog A to symbol
I know the version is so old that its frustrating to use, anyhow the error is still existing, when I initiate the instance in the schematic it doesnt show CDF parameters. But I still went on to get the netlist from spectre and attached is the error I got. This the same problem Im facing for a very long time. Thank you so much Andrew for such prompt replies and valuable guidance. Warmest Regards Shobhit
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Forum Post: RE: Cadence Specctra (Allegro Router) 17.2 Issues in Windows 7 Pro (64 bit)
Hi mcatramb91, Not exactly. I get the same behavior in Windows 7 whether I start Specctra (Allegro Router) within an Allegro layout session or start Specctra by itself...makes NO difference in that I cannot quit the Specctra application without going to the Windows 7 Task Manager and terminating the Specctra application. Also, while I am in a Specctra session (with or without Allegro layout running), the operation is slow and "sticky" in that any menu item I use seems to hang for several to 50 seconds! This tells me that there must be some kind of software driver incompatibility either within Windows 7 or with the Nividia graphics driver with the Specctra application. Again, as mentioned earlier, NO issues at all in my VMware Workstation Pro virtual machine running Windows 10. One more thing, I have run Specctra previously in versions 16.2 and 16.6 (same Nividia graphics card) without any issues in Windows 7 and Windows 10, so there is definitely something different about how Specctra in version 17.2 works within Windows 7. CT
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Forum Post: RE: Export DXF and ODB through skill
Hi Dave, i try a2dxf but i not able to change the cnv file according to film user wanted to convert to dxf. for example: initial user manully use ABC.cnv to convert drill film to dxf(user can edit the cnv and save) second time user to ABC.cnv to convert soldermask film to dxf.(dxf that export is in drill film as axlRunBatchDBProgram did not include the parameter to edit the contain of cnv) any idea how can i edit the .cnv file according to user selected film? Regards, Eugene
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Forum Post: RE: Export DXF and ODB through skill
may i know where can i find brd2odb command line arguments file?since it is from mentor. I not able to find inside batchhelp folder Thanks alot Eugene
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Forum Post: Monte Carlo simulation results have difference even in ideal circuits
Hi everyone, I'm now running an analog-to-digital converter project, all the circuits are ideal (vcvs built op-amp, switch, quantizers...) to verify the function. So if I run MC mismatch using ADE-XL for this ideal circuits, every time I got the same waveforms and final Quantizer output code, this is what I expected. The problem occurs when I started to put some real circuits in the schematic, for example just an inverter in standard library (the inverter is not connected to anything, just put in the schematic) , and now for MC simulation the results are different, some nodes' waveforms now start to have slightly difference, but I don't know where those mismatches come from.
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Forum Post: RE: Simulation and PEX
Hi Allen, It won't impact the simulation, since that's just using the netlist that was produced prior to the simulation starting. However, it might affect your ability to probe signals within the Calibre extracted view after simulation, since the probe points don't match the netlist. However, if probing outside of the pex view, you would be fine. Regards, Andrew.
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Forum Post: Problem with AMS Netlister when using pPar function
Hi all, I have trouble with netlisting problem of AMS simulator. The symptom is like below; When I start simulation using ADEXL, it stops at netlist; It seems that AMS netlister have a problem when I use pPar function. I simulated AMS not using pPar function, then, the simulation is done well. I want to use pPar function in AMS simulation, too. Please help me. I'm using IC6.1.5_ISR17, MMSIM ver12.1, and I use 'setenv CDS_AUTO_64BIT ALL' option in cshrc.
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Forum Post: QRC extraction error, incorrect connectivity (input from Calibre LVS)
Hi there, I have encounter some error message as followed, inter N_0LVT_0G_0P NPLY_0LVT_0C -t N_0LVT_0G_0P_NPLY_0LVT_0C_butt:edge ERROR (INTER-52012): Cell mj18a02_l_rm2to4: two nets 229 and 140 touch at (0.288,0.51) on layer 'N_0LVT_0G_0P' possible cause: incorrect connectivity It does not give me any clue that what should i do to resolve the issue, and amend the GDS is not possible from my side, i have read something onto 'GRAYBOX mode' in the support page, but seems like my attempt with that is failed to resolve the issue. Please kindly help. Regards, MF
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Forum Post: RE: Documentation error for awvPlotWaveform function in Virtuoso Visualization and Analysis XL SKILL Reference manual
The best way to do it is to open a case with Cadence customer support, and the assigned AE will verify if the latest version of document also has the bug and can open a CCR on your behalf if needed. You can then monitor the status of the CCR through your account.
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Forum Post: RE: STEP Question
There is a steppath variable (same principle as psmpath or padpath) that tells PCB Editor where to look for Step Models. You need to either talk to your mechanical team for STEP models or look at free resources such as 3dcontentcentral.com or ultralibrarian.com who supply step models. Many component manufacturers supply step models as well so build up a library of them. There are a few supplied in C:\Cadence\SPB_17.2\share\pcb\examples\step there is a workshop.zip that has a few samples as well.
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Forum Post: RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
Locate your HOME directory (so type %HOME% into the address bar of Windows explorer). In here is a pcbenv folder, rename this to pcbenv_old then try and run the tools again. if this solves your issue you will need to redefine your setup (so padpath, psmpath etc) and any shortcut keys you may have. If it doesn't post back
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Forum Post: RE: Documentation error for awvPlotWaveform function in Virtuoso Visualization and Analysis XL SKILL Reference manual
Saloni's absolutely right, but I pinged the tech pubs team (as it's just a single character fix) and they're going to correct it. Saves everyone (you, support and R&D) a bunch of admin work. In general though a case (I think you can use feedback from the manual on support.cadence.com to do it too, which is also a fairly easy solution). In fact in the time it's taken me to write that first sentence, I've just heard that they've already fixed it ;-) . It should be in the IC617/ICADV123 ISR20 hotfix. Regards, Andrew
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Forum Post: RE: Allegro 17.5 Padstacks - Rounded rectangle for IPC SMD Footprints - Corner radius value recommendation ?
I think you mean 17.2 but in any case if you look at something like PCB Libraries, this uses the IPC standard to build parts and for R's and C's it seems to be using 0.25mm for the radius based on a pad size of 1.16 x 1.82. If you generate a SOIC pad the radius is 0.1 based on a pad size of 1.36 x 0.39. Not sure that helps much but I did have a quick check of IPC7351B and can't see any reference to a preferred value.
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Forum Post: generating Xnet from netlist or inside constraint manager
Hi to all, i need to create some Xnet inside my pcb but the 2 nets (or more) are divided Not from a capacitor or resistor but with an IC. so ask: is there is a possibility to generate these Xnets from a description in the Netlist or adding some attributes in the nets, or adding them directly on some way inside the Constraint Manager? any reply will be appreciated. have a good day to all. Livio
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Forum Post: RE: single layer pcb
The only solution I've found is to manually delete the layers in the cross-section diagram. The whole thing seems wonky
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Forum Post: Ocean command to access the result stored during Monte-carlo Simulation
Hello, I am doing the monte-carlo simulation using ocean Script. Whenever, we run the monte-carlo simulation and when it gets completed results of that run got stored in a separate folder with name "adexl" in the current working directory of the same cell view folder. Is their any command in ocean that allows to access the result stored, so that further analysis can be done on that without performing the monte carlo simulation again??
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Forum Post: RE: STEP Question
My proceedure (16.6): 1. Duting the footprint creation I add a max height property to the package place bound geometery. If you edit properties on this shape you will see the fieald. This will so the package heigth without a step model. look at the 3D view before and after doing this, you will see what I am referencing, note you must not have any feature selected when looking at the #D view. 2. I map the Step model into the pcbfooitprint file, and I aligh it to the package geometery, insuring pins line up. You can rotate and move the step model in all axis. So the step models will be brougt hinto the layout with the footprints, of course the paths for your library need to be setup up correctly.
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