Hello exports, I guess I might need some parameters to Spectre to avoid skipping value points. By older version it gives good staircased signal (from VerilogA) but in newer version it misses several stairs. Any clue what I should do to make the simulator not skipping? the good staircase signal in older Spectre simulator: the bad staircase signal with several stairs missed in newer Spectre simulator: thanks, David
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Forum Post: Spectre skipping points
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Forum Post: RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
Man you're good. I did as you described and my designs seem to open normal again. Then I remembered I had added a skill from 2013, Logomaker, so I thought that may have something to do with it and I went back to the original pcbenv folder and designs are still opening fine. Could that have reset something else? Either way, I'll continue to monitor and post back if things go south again.
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Forum Post: RE: Spectre skipping points
Hi David, Without knowing anything about the version you're using, the model, the circuit, or the simulation settings, it's virtually impossible to say. However, the delta in the output signal is very small - perhaps it's below reltol (the default reltol on a 5V signal could cause changes smaller than 5mV to be ignored if using reltol=1e-3 and errpreset=moderate) - here your output steps were only 10uV in a 5V signal. So it might be an accuracy control thing, or it could be all number of other issues - there simply isn't enough information to diagnose the issue. Regards, Andrew
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Forum Post: RE: generating Xnet from netlist or inside constraint manager
You could use an ESPICE model to define the Pin Pair that will act like a pass-thru on the IC, the same way it is done with a Discrete component Analyze > Model Assignment Select the IC on the canvas and select the Create Model button Select "Create ESpiceDevice model" and Click OK Define the pass-thru pin number sets (From To From To) A value of 1 10 8 15 will create pass-thru between pins 1 and 10 and 8 and 15 to form XNets
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Forum Post: RE: Spectre skipping points
hi Andrew, totally understand and was wondering if some quick clue, not expecting exact answer yet. I guess I might have to create a small test case to reproduce and get back to you. P.S., the Important parameter values from prompt: start = 0 s outputstart = 0 s stop = 1 s step = 1 ms maxstep = 10 ms ic = all useprevic = no skipdc = no reltol = 100e-06 abstol(V) = 1 uV abstol(I) = 1 pA temp = 27 C tnom = 27 C tempeffects = all errpreset = conservative method = gear2only lteratio = 10 relref = alllocal cmin = 0 F gmin = 1 pS thanks, David
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Forum Post: RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
It went south. I was working on a design and closed PCB Editor in order to undo some work that ctrl-z couldn't undo. When I reopened the file, it immediately closed. I'll go back to your suggestion and see how that works.
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Forum Post: RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
Moments after my last reply, it went south with the new pcbenv folder. Any other suggestions?
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Forum Post: RE: Verilog A to symbol
Error found by spectre in `PCNFET', during circuit read-in. ERROR (SFE-23): "/home/v45960/shobhit/nano_model_35/CNFET/PCNFET/veriloga/veriloga.va" 94: The instance `XPCNFET_L2_edge' is referencing an undefined model or subcircuit, `PCNFET_L2'. Either include the file containing the definition of `PCNFET_L2', or define `PCNFET_L2' before running the simulation. ERROR (SFE-23): "/home/v45960/shobhit/nano_model_35/CNFET/PCNFET/veriloga/veriloga.va" 101: The instance `XPCNFET_L2_midd' is referencing an undefined model or subcircuit, `PCNFET_L2'. Either include the file containing the definition of `PCNFET_L2', or define `PCNFET_L2' before running the simulation.
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Forum Post: RE: STEP Question
Thanks for the reply. This will be my next step (no pun intended) to start associating the models with the library parts. Your tips will help! Tom
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Forum Post: RE: STEP Question
Hi Steve, Mechanical team...... you're funny..... no mechanical team here....... I figured that I would end up needing to source the .stp models myself. I have downloaded a few from Ultra Librarian and successfully imported and associated them with some of the parts on the board. The issue now is that they don't show up when viewing the board in the 3D viewer. If I export the pcb STEP file and use an external viewer they show just fine. What is the trick to getting them to show in the PCB Editor 3D viewer? Tom
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Forum Post: RE: STEP Question
BTW a great source for 3D Step models is here: http://www.3dcontentcentral.com/ I output the STEP from Allegro once the board is designed so we can verify mating of boards and created 3d printer enclosures. Here's and example: community.cadence.com/.../ZLE38000_2D00_006_5F00_AL_5F00_Rev1_5F00_with_5F00_Ardui.pdf I use solidworksfor the mating and step module creation whne there is none for the parts I need. Kind Regards, Wild
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Forum Post: RE: STEP Question
Turn on your place boundtop
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Forum Post: Collision Detection with PCB in Allegro 3D Canvas
In Allegro 3D Canvas, is there anyway to include the PCB in the Collision Detection calculation? It seems like it detects collisions with symbols just fine like the components on the board and the mechanical enclosure, but it does not include the PCB itself. Obviously, if the PCB is colliding with the enclosure that would be problematic so I was just wondering if I was missing something here or if there is another way to accomplish this.
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Forum Post: Reversing the contents of an expanded bus in VIVA
In VIVA, when you expand a bus it yields (top to bottom) bus ... bus . I need the order reversed i.e. MSB on top. Is this possible? And so we come to the part where you chime in and say "no, you lose".
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Forum Post: RE: Reversing the contents of an expanded bus in VIVA
Just providing some further clarification. I have declared a bus as follows: dout_bus = awvCreateBus("dout_bus" list( \ L("/dout ") L("/dout ") \ L("/dout ") L("/dout ") L("/dout ") L("/dout ") \ L("/dout ") L("/dout ") L("/dout ") L("/dout ") \ L("/dout ") L("/dout ") L("/dout ") L("/dout ") \ L("/dout ") L("/dout ") L("/dout ") L("/dout ") ) "Binary") The L() function is something I wrote to convert a Verilog-A waveform into a digital waveform. When the bus is collapsed I see the contents in HEX and correctly derived from dout ... dout . So here's the part I think isn't so intuitive. When I expand the bus it shows me the waveforms: dout_bus[0] dout_bus[1] ... dout_bus[17] however the waveforms associated with each of the above are actually dout dout ... dout and that makes me confused. Am I doing something dumb?
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Forum Post: RE: Allegro 17.5 Padstacks - Rounded rectangle for IPC SMD Footprints - Corner radius value recommendation ?
Hi Steve, 17.2... That info helps, I too did some hunting around but came up kind of short. I think for the moment I will just abandon the idea and go with the standard. I do see a case in using them in particular when it comes to the solder stencil and having a pad that closely matches that for which paste gets applied to. Thanks, Paul.
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Forum Post: RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
I know it is a little extreme, but could you try renaming the 17.2 folder (RMB > Rename) in the registry and restart the PCB Editor. PCBENV Folder is not the only place were the configuration is stored, data is also in the Registry. Renaming the folder will allow it to regenerate a clean registry folder. Worth a shot. Registry location: HKEY_CURRENT_USER \ SOFTWARE \ Cadence Design Systems \ 17.2
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Forum Post: RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
I wonder if it is some sort of wierd bug related to the auto save user preferences. Have a look in the User Preferences editor and do a search for save. A bunch of preferences should show up. On my system here all autosave preferences are un-checked "Default" and "ads_autosavers" has a value of 0 Maybe worth a shot ? Paul.
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Forum Post: RE: Cadence Specctra (Allegro Router) 17.2 Issues in Windows 7 Pro (64 bit)
Folks, Found the problem. It appears that the latest Nvidia drivers downloaded today seem to have eliminated the problem. Therefore, it was the previous Nvidia graphics driver that was causing issues with the Specctra program. That also explains why I did not have the same issue inside a Windows 10 virtual machine as that environment uses a VMware graphics driver. Hope this helps anybody else that might experience that issue. CT
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Forum Post: ADEL - skill : adding signals on the list of outputs to be plot/saved
Hi, In ADEL I want to modify the list of outputs to be plot/saved using skill. Is there any skill procedure to to this? Assume that the simulator is spectre, and the proper session is open in ADEL. Thank you, Marcel
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