Look for the Brd2odb_help.pdf in the directory where the ODB++ translator executable of Mentor is placed. In the PDF you have a section 'Using Command Line Parameters:' The command line is 'brd2odb [parameters] ' You can see which commands are actually used, put this in the Allegro command prompt: set wait_debug Then the axlRunBatchDBProgram() commands are echoed in the commandline. The same is valid for the DXF export. For a simple DXF export to give you a head start: dxfFile = "dxf_output" fcnv = "DXF_mapping" layer = "TOP" p = axlDMOpenFile("ALLEGRO_CNV", fcnv, "w") fprintf(p "#This is the Layer Conversion File used for\n") fprintf(p "#importing DXF data into Allegro/APD.\n\n") fprintf(p "#CLASS! SUBCLASS! DXF_LAYER!\n\n") fprintf(p "BOARD GEOMETRY!\n") fprintf(p " CUTOUT! OUTLINE!\n\n") fprintf(p "BOARD GEOMETRY!\n") fprintf(p " DESIGN_OUTLINE! OUTLINE!\n\n") fprintf(p "PACKAGE GEOMETRY!\n") fprintf(p " ASSEMBLY_%s! PACKAGE!\n\n" layer) fprintf(p "PIN!\n") fprintf(p " %s! PIN!\n\n" layer) fprintf(p "REF DES!\n") fprintf(p " DISPLAY_%s! REF_DES!\n\n" layer) fprintf(p "#END\n") axlDMClose(p) sprintf(str "a2dxf -$ -u MM -a 3 -f 12 -c L \"%s.cnv\" \"%s/%s_%s.dxf\" %%s" fcnv getWorkingDir() dxfFile layer ) res= axlRunBatchDBProgram("Generating DXF File... " str ?noLogview t ?warnProgram t ?noExitMsgs t) deleteFile(strcat(getWorkingDir() "/" fcnv ".cnv")) Kr, Bram
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Forum Post: RE: Export DXF and ODB through skill
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Forum Post: RE: Cadence Custom Layout for beginners -RF IC design
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Forum Post: RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
Give Mike's registry suggestion a try but just as an FYI, instead of closing PCB Editor, if you need to revert to a previously saved version just type reopen at the command line followed by return and the saved version is reopened.
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Forum Post: RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
Good to know. My command line skills are certainly lacking.
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Forum Post: RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
My auto-save is off as well, but I could try and turn it on and see if my behavior changes. I'll try that after Mike's suggestion
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Forum Post: RE: PCB Editor Immediately AutoSaving and Closing When Opening Design
I tried your registry fix and the pcbenv rename together. I'll give it some time and report back.
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Forum Post: How to save global routing output (ie. guide for Detailed Routing)?
Hi, I want to execute global routing and export the global routing output in a file, probably a .guide file such as the ones in the benchmarks of ISPD 2018 Contest ( http://www.ispd.cc/contests/18/index.htm ). By global routing output I mean the sets of rectangles that act as guides for each net in detailed routing. I am currently using Innovus tool and I didnt find the option to do it. The closest I've found is to execute Early Global Routing and then using the "saveRouteGuide" command, but this seems to be a pre-step of global routing.
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Forum Post: RE: Verilog A to symbol
I tried this in IC5141 yesterday (admittedly I was using MMSIM11.1 rather than MMSIM7.2 that you were using, but I doubt that makes a difference) and it works fine. I'm using subversion 5.10.41.500.6.151). In terms of the CDF parameters being shown, this works fine - you just have to click on the "CDF Parameter of view" cyclic field to show them: Note that you should check your netlist (Simulation->Netlist->Display and see if you are getting the three ahdl_include lines). If you're not, maybe you're using an old subversion of IC5141 which had a bug? If so, what are you using (type getVersion(t) in the CIW to get the subversion and post it here). Have you removed the include of the lower level modules in the higher level modules? Regards, Andrew
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Forum Post: RE: SKILL function for getting point ID (or netlist directory) in ADE XL
Hi, Try this: session=axlGetWindowSession() historyName=axlGetHistoryName( axlGetCurrentHistory(session)) rdb=axlReadHistoryResDB(historyName) foreach(test rdb->tests() printf("Point %d Corner %L Test %s | The netlist directory is : %s \n" test->pointID test->cornerName test->name strcat( test->resultsDir "/netlist")) ) test->resultsDir returns the results directory of each sim point which is the dir that includes the netlist and psf folders. Using strcat I have added '/netlist' to point to the netlist directory. Regards, Dimitra
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Forum Post: RE: Reversing the contents of an expanded bus in VIVA
No, you're not doing something dumb. It doesn't really know what the original signals were once the bus was created - it just outputs them in a fixed order relative to the bits in the bus. I agree, it would be a good idea to have control over the order in which the bits were expanded, so you should contact customer support to request this (I didn't find any existing requests, but that doesn't mean it's not a reasonable request!) Regards, Andrew.
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Forum Post: RE: how to open a .brd file in capture
ty for your reply but i want to run simulation in capture of a .brd pcb file. is it possible?
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Forum Post: Generating a spectre netlist(.scs) with a corner conditions in command line
I've seen answers on the support forums regarding the generation of .scs files using the command line, but I couldn't find any answers regarding the creation of spectre netlists for a corner condition. Any suggestions?
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Forum Post: RE: SKILL function for getting point ID (or netlist directory) in ADE XL
Thank you for your suggestion. It looks like your code will return full list of netlist for each design points. However I think I need something slightly different. I am making a custom function that will show the result in ADE XL result window. For example, I would like to get something like this in ADE XL. Point VDD Process corner Power Output duty cycle Netlist Directory Some value from a file in the netlist directory 1 1.6 SS 2.4 45 [???] [???] 1 1,6 FF 2.5 55 [???] [???] 2 1.8 SS 3 47 [???] [???] 2 1.8 FF 3.1 54 [???] [???] 3 2 SS 4 49 [???] [???] 3 2 FF 4.3 51 [???] [???] In this example, I am sweeping three different VDD in two different process corners. I would like to measure three values in this example. I can use pre-defined Waveform Calculator function for simple expressions like "Power" and "Output duty cycle". I also would like to have some custom function that will read a certain file in the netlist directory and show certain value from that file in the same ADE XL window. Maybe I can use your code to generate separate text file that contains all the result. However I would need to open the result file after each simulation run, and I'd like to avoid that. Again, thank you very much for your answer.
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Forum Post: Problems with simulating counter chips
hi there i'm having trouble on counter simulation. where can i find a counter library with psipce model to run? for example i want to simulate cd4060 or 74867, what should i do? many thanks
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Forum Post: PDF Export--> Name duplicating
Hi, I am trying to export pdf in Allegro 17.2 its getting successfully exported however file name is duplicating as shown below. Could someone please help me to solve this problem? "SENSOR_PARA_REV0_SENSOR_PARA_REV0.pdf" Thanks, Sanjeev
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Forum Post: RE: Generating a spectre netlist(.scs) with a corner conditions in command line
Unfortunately your question is extremely open ended and not very precise. Are you asking about how to learn the syntax of writing spectre netlist by hand? Are you asking how to create a netlist from a Virtuoso schematic for spectre using some kind of command-line method? Are you asking how to use OCEAN? The Forum Guidelines suggest you ask questions which are clearly stated with sufficient information (such as the tools you're using and the versions) - and unfortunately you didn't provide any of this, so it's really hard to answer. You also posted this in the Mixed-Signal Design forum, so is your question related to AMS (Analog Mixed Signal - i.e. mixed analog/digital) simulation?
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Forum Post: Packaging custom IP with block designs
Hi, I've created a custom IP block using the 'Create and Package IP -> Create a new AXI4 peripheral' flow. The peripheral works fine, so I added my own custom HDL code, and after that it still works fine using the following flow for making changes: 1. Re-package IP using the IP-XACT XML file interface. 2. Close IP project, let Vivado update the design where the IP is instantiated. 3. Run the IP report to make sure things went as expected, then run sim/synth/implementation. 4. When I need to make changes to the IP, right-click and 'Edit in IP packager' 5. Make changes and go to (1). Based on what I can gather from reading forums, documentation and answer records, this is the way Vivado is designed to work for this task. So first of all, is this the correct flow for create-package-edit-repackage of custom IP? I didn't find the right solution from the Internet. References: https://forums.xilinx.com/t5/Design-Entry/Packaging-custom-IP-with-block-designs/td-p/558247 Video marketing studio .Thanks
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Forum Post: "Open IP example design" not using the requested HDL?
Hi, I'm generating some Ethernet IP on 2015.4 (10G Ethernet PCS/PMA (10GBASE-R/KR)), on two different computers. The xci requests Verilog output. On one computer, I actually get Verilog output. On the second computer, Vivado generates VHDL output, and modifies my xci to change the requested HDL from Verilog to VHDL. Does anyone have a fix for this? It only happens on the Vivado GUI for "Open IP example design" - running a tcl open_example_project does the right thing. For More Details: Creative video service
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Forum Post: IPI - Create IP from a block design
Hi, I followed along hte tutorial in UG995 (2015.2), which results in a block design as in the attached screenshot. Q: Is it possible to pack this entire block diagram into an IP block, so I can re-use it in other designs, to have a hierarchical design aproach in IPI. So the resulting IP block would have the ports : S00_AXI, ACLK, ARESTN, ext_spi_clk, iic_rtl, uart_rtl and spi_rtl. Q: if so, how do I pack this? I tried to pack it as a project and pack it as a directory, but without real success. Is there an example on packing a BD For More Details: Explainer Video Company
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Forum Post: Knife IP and Clones Explained
Hi, When reading many forums and sites regarding gear I see a lot of misconceptions regarding trademark infringement and IP in general. I have a little knowledge on the topic so I figured I would write up something to clarify terms and explain why any counterfeiting hurts consumers, companies, and the market. This has been a hot topic in another thread so I figure the timing might interest some of you. IP is "intellectual property." It is different from physical property. If you make a chair, it is easy to maintain control over the physical chair. If you come up with a great song, design, logo, etc, it can be duplicated for pretty much no cost. In America we have laws to protect IP to protect consumers and innovators. For More Details: Motion graphics video animation agency
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