Hi I have a circuit with differential output and would like to run differential load pull. How should I set up the simulation? In single ended mode, I use the PSS simulation and a PortAdapter block, finally plotting the constant power contours (selecting the input terminal to the PortAdapter itself). I am not sure how to properly set-up the simulation for the differential. Can you help, please? Many thanks. Luca
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Forum Post: Load pull - Differential
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Forum Post: RE: Ignore the lower or uppercase in regular expression.
Hi Andrew, Sorry, I have to ask your help again. Can you tell me where I can find the doc for pcreMatchp's usage? Format and parameter. I am using Allegro, I can't find any help in 'Skill Language User Guide'. BTW, if pcreMatchp can match a list? I mean when I have several keyword -- "^HT" "^HEIGHT" "^HGT" "MAX HT", and if can I use one pcreMatchp to match text and ignore the lowercase and uppercase? Sorry to bother you, appreciate your help Regards, Jason
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Forum Post: RE: pass variable value to procedure name
Thanks a lot Andrew! In above case we passed "MET1" string to the procedure as metConvert("MET1"), what if we need to pass 'list' instead of 'string' ? what is the change we need to do in below command, sprintf(nil "metConvert(%L)" metArray) of hiSetBindKey command. Thanks and regards, Basavaraj Tambur
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Forum Post: RE: detecting process corner from within verilogA model
HI Saloni, As per your suggestion I set the option redefineparams = error instead of warning and i get the following error: Parameter `corner' was previously defined. Please try to add `+spice' in command line or option `redefinedparams' in netlist to avoid these type of errors. I am still searching for the solution to get override the ADE-L value with Model file values but no solution yet. Thanks! Shreev.
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Forum Post: auCDL, question about ansCdlSubcktCall netlist procedure!
Hi all! I have a question about termOreder when we are using ansCdlSubcktCall netlist procedure. I have device ptap1. There is auCdl section of this device: cdfId->simInfo->auCdl = '( nil netlistProcedure ansCdlSubcktCall instParameters (r w l) propMapping (nil r R) namePrefix "X" modelName "ptap1" termOrder (TIE SUB) componentName "resistor" ) and I've created test schematic (see attached picture) And when I export this schematic in cdl, we have following netlist: .SUBCKT ptap1_a a1 *.PININFO a1:I XR0 net02 a1 / ptap1 r=262.847 w=780.00n l=780.00n MN0 net4 net6 net5 net02 sg13_lv_nmos m=1 w=150.00n l=130.00n ng=1 .ENDS .SUBCKT ptap1 TIE SUB .ENDS The question is, that in auCdl section we have termOredet TIE, SUB (and auCdl view also) and I expected, that in my netlist I'll see XR0 a1 net02, but in real netlist I see: net02, a1. If I will use ansCdlCompPrim netlist procedure - all works fine: .SUBCKT ptap1_a a1 *.PININFO a1:I RR0 a1 net02 $[ptap1] MN0 net4 net6 net5 net02 sg13_lv_nmos m=1 w=150.00n l=130.00n ng=1 .ENDS .SUBCKT ptap1 TIE SUB .ENDS Could you pls. tell me, how to resolve this issue?
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Forum Post: RE: Export DXF and ODB through skill
It should be present when you install the Allegro ODB translator. (look in the C:\MentorGraphics directory, or in the c:\program files) Here it is, but be aware that it is not the latest version. community.cadence.com/.../Brd2odb_5F00_help.pdf
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Forum Post: RE: ADEL - skill : adding signals on the list of outputs to be plot/saved
I share your pain on this one! There are a couple of things you can try though. To get a list of expressions, both of these seem to work: win = hiGetCurrentWindow() sessId = sevSession(win) sessId_str = symbolToString(sessId) ;; needed due to a bug that was only fixed in the last month or so in the latest IC617 ISR session = asiGetSession(win) ;; this gives you a list of sevOutputStruct my_outputs = asiGetOutputList(session) ;; this gives you a list of lists, each sublist is list(name expression) my_outputs2 = sevGetExpressions(sessId_str) Those functions are documented as public so it should be ok. Don't ask me to explain fully the difference between a session from sevSession() and the one from asiGetSession() because I'm not clear on that. for setting outputs, I've tried things like this which mostly work but the last one you add won't have the plot box checked. You can work around that by adding one more call to sevAddExpression() after you've added the ones you want. sevAddExpression is in the manual so I guess it should be ok to use but I get the distinct impression that it is not used much by users because it is not so friendly. For example, I couldn't find a way to change an existing expression and you have to jump through some hoops to get the plot/save checkboxes to update the way you might want. session = sevSession(hiGetCurrentWindow()) r = sevAddExpression(session "MyOutputName" "VT(\"/out\")") ;; documented in the manual cadr(r)~>plot = t ;; not documented so it may change in the future r = sevAddExpression(session "MyOutputName2" "VT(\"/out2\")") cadr(r)~>plot = t ;; dummy call (won't overwrite, but will trigger the form to redraw and fix the plot box). This is also not documented behavior so we can't count on it. sevAddExpression(session "MyOutputName" "dummy_expression") You can also jump through some hoops trying to use get_pname(session->window->hiForm) which gives you something like "sevWindowForm3". You'll need to extract out the "3" (or whatever number) part, save to form_number, and then do something like: myForm=evalstring(sprintf(nil, "sevOutForm%d", form_number)) sevSetTableItem(myForm->outListBox expression_number 2 "true") ;; to enable plotting sevSetTableItem(myForm->outListBox expression_number 3 "true") ;; to enable saving expression_number needs to be set to the index to this particular expression in the table. You can get at that by using sevGetExpressions(). but... all of this hacking of forms seems like a good way to have code that may work for a while on the current release and then possibly fail in unexpected ways on the next release because I don't think we (users) are really supposed to be poking around in the internals of the form. This would be a nice enhancement though. In general I feel like there could be a much nicer API for ADE-L which probably carries over to Explorer. Personally, I'd love to have something for both design variables and outputs where there was a simple query by name: out_val = myGetOutputByName("FOO") and a simple way to set it along with maybe some flags to overwrite if it already exists and easily set the save/plot states. Good luck! -Dan
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Forum Post: Placement Quickview not showing pads
Hello, I am a newbie to PCB editor. I have seen videos in which, when placing components manually, in the placement pane's "quickview window", you can see the outline of the part and the pads. I am only seeing the part outline and silkscreen, no pads. How do I see the pads in the quickview window? Thanks, Emmett
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Forum Post: RE: auCDL, question about ansCdlSubcktCall netlist procedure!
I think I've already found an answer, need to the .simrc file add following: auCdlCDFPinCntrl = t.
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Forum Post: RE: detecting process corner from within verilogA model
Hi Shreev, Can you paste here the header of your Spectre netlist? I'd like to see the part where the global variables are being defined and model files are called. As an example: // Generated for: spectre // Generated on: May 16 16:56:59 2018 // Design library name: testLib // Design cell name: BUF_sim // Design view name: config simulator lang=spectre global 0 parameters Vsup=1.8 Vgnd=0 Vin=1.8 include "gpdk090.scs" section=NN Regards, Saloni
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Forum Post: RE: ADEL - skill : adding signals on the list of outputs to be plot/saved
Hi Dan, With Explorer and Assembler, there's a new simplified interface (the sev functions are not properly documented in my opinion, with quite a lot of holes. Plus you were using a number of private capabilities there). There's maeAddOutput for example. The results with Explorer and Assembler are always in the RDB, so getting the results are more consistent. So in practice we're moving towards an API that works with Explorer/Assembler as the way forward, rather than adding something for ADE L which then works in the others. Architecturally it makes more sense to focus on the Explorer/Assembler way as that's the way forward. There may still be gaps in the "mae" APIs - but there's general willingness to fill those gaps. Regards, Andrew.
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Forum Post: RE: detecting process corner from within verilogA model
Following on from Saloni's suggestion, if the parameters are after the model files, perhaps you have: envSetVal("spectre" "netlistModelFileFirst" 'boolean t) in your environment. Suggest you try calling: envGetVal("spectre" "netlistModelFileFirst") and seeing if that returns t rather than nil (which is the default). Regards, Andrew.
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Forum Post: RE: pass variable value to procedure name
Well, assuming that metArray is a list (note, do not confuse lists with arrays; they are not the same thing as lists are sequential, ordered structures, whereas arrays allow random-access), then probably you'd do: sprintf(nil "metConvert('%L)" metList) if a literal list is OK, or: sprintf(nil "metConvert(list%L)" metList) Regards, Andrew.
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Forum Post: RE: Ignore the lower or uppercase in regular expression.
Hi Jason, A few things: These functions are covered in the SKILL Language Reference - which is also in the Allegro release. It's in the doc directory, under sklangref/sklangref.pdf and should be findable in cdnshelp, or at Cadence SKILL Language Reference (6.1.6) on the support site (I found this by navigating to the SPB17.2-2016 release manuals) There's pcreMatchList, but that's not what you want - that's to match against a list of candidate values to return which elements in the list matched the pattern. You appear to want a list of patterns. Rather than providing a list of patterns, you could just use a group of alternative patterns with a pipe character: pcreMatchp("(^HT|^HEIGHT|^HGT|MAX HT)" text pcreGenCompileOptBits(?caseLess t)) Regards, Andrew.
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Forum Post: RE: Ocean command to access the result stored during Monte-carlo Simulation
What you can do is: openResults("path/to/simulation/ libName / cellName / adexlViewName /results/data/ MonteCarlo.14 /psf/ testName ”) then you should be able to run the code at the end of your OCEAN XL script, as it’s pointing at the overall set of results. Obviously you need to set the libName, cellName etc and the right history name - the bits in italics above, but other than that it should be straightforward. Regards, Andrew.
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Forum Post: RE: how to append a constraint with cstCreateConstraint
Do you have a cutClass with (0.04 0.04) dimensions defined in the cutClasses section of the tech file? If not, it won’t add the constraint and you should see something like: *WARNING* (CST-5305): Illegal cut class value (0.4 0.4) specified. Specify a legal value. If I give a legal value (i.e. a pair of values for which there is a cutClass defined for the via layer in question) then I can successfully add the constraint using the code you gave. Regards, Andrew.
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Forum Post: RE: Generating verilog netlist from schematic
Can you clarify what you mean here? Perhaps give an example of what the schematic looks like, what the portion of the netlist looks like, and what you want? Generally posting on the end of an old thread isn't a good idea (even if it was yours) because it means it's less clear what topic the question was on and it makes it harder for somebody to reuse the info. Regards, Andrew.
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Forum Post: RE: Defining waveform thicknesses and colors on a white background in VIVA
I don’t believe there are any controls to alter the definition of the line thicknesses in ViVA. This is the first I’ve heard of anyone objecting to the default definitions (I didn't find any requests to control this so far) - if you need control over this, it would need an enhancement request. Also a bit surprised about your comment about the default colours being lousy; we actually do automatic contrast adjustment in ViVA when altering the background colour - I often set my background to white because I frequently give demos on projectors, and a black background is often bad on a projector, but the colours usually are good when projected with a white background without me needing to adjust. Still, each to their own - that’s why we allow you to control it! Regards, Andrew.
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Forum Post: RE: Converting Waveform to list
Hi Savino, Are you using the “Hysteresis Sweep” checkbox on the dc analysis, or are you simulating the hysteresis in some other way (I’m assuming you’re using spectre). The Hysteresis sweep produces a single waveform (not a family). Probably would have to have a clearer example of precisely what you're doing in your script - perhaps this would be better handled via customer support ? Regards, Andrew.
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Forum Post: RE: display signals in a new strip from Ocean script
Hi David, I just tried this (sorry about the delay in getting to this question). It works fine for me - using IC617 ISR19. With the envSetVal, just calling plot with no ?strip argument adds to a new strip each time. Regards, Andrew.
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