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I don’t think anything has changed related to this. Regards, Andrew.

[quote userid="377063" url="~/cadence_technology_forums/f/custom-ic-design/38788/aucdl-question-about-anscdlsubcktcall-netlist-procedure/1355097#1355097"]I think I've already found an answer, need to the .simrc file add following: auCdlCDFPinCntrl = t.[/quote] Yes, that's the answer. Andrew.

Hi Saloni, Thanks for your reply. First of all I would like to mention here that I am using the AMS simulator for this purpose. If I understood correct I should simulate my Verilog-a code using AMS simulator. As you can find the AMS netlist as follows: // Design library name: wk_BG // Design cell name: corner_tb // Design view name: config // Solver: Spectre `include "disciplines.vams" `include "userDisciplines.vams" // Library - wk_BG, Cell - corner_tb, View - schematic // LAST TIME SAVED: May 16 17:40:38 2018 // NETLIST TIME: May 16 17:55:54 2018 `timescale 1ns / 1ns `worklib wk_BG `view schematic (* cds_ams_schematic *) module corner_tb (); corner #( .getcorner( cds_globals.corner ) ) I1 ( .Y(my_corner), .A(net1)); endmodule `noworklib `noview // END AMS-OSS Netlist // Verilog-AMS cds_globals module for top-level cell: // wk_BG/corner_tb. // Generated by ADE. // Cadence Design Systems, Inc. Thanks.

Hi Andrew, Yes According to your suggestion my environment setup is : envGetVal("spectre" "netlistModelFileFirst") = nil Which I setup using envSetVal("spectre" "netlistModelFileFirst" 'boolean nil) Thanks

Although that's not going to be the issue here - it's a shame you only just mentioned the rather important fact that you're using AMS! Verilog-A can be simulated with Spectre. Verilog-AMS however requires AMS (you can of course simulate Verilog-A too, but there's no requirement to use AMS for VerilogA). I'm not sure you can have spectre parameters in model files overriding design variables netlisted into the cds_globals module - they are two different namespaces in the simulator. I'm not aware of a way around this. There might be a way by having the VerilogAMS variable use $cgav (i.e. $cds_get_analog_value) to look up a spectre parameter. I've never tried this - this is just a wild guess based on a quick read of the manual. I'll see if Saloni has some bandwidth to try this (I'm travelling for a few days so definitely don't). Regards, Andrew.

cool, thanks Andrew.

This is a bug in some versions of 17.2-2016, fixed in hotfix 38, currently hotfix 39 - 17.2-2016.s039

Hi Dan, Thanks a lot for the hints. The original request that I had was next one: people will provide a list of signals that must be in the save outputs, and if there are some signals that are not in thelist they need to be added . But for now, because there is no API, we decided to implement something else: compare the initial list with what is already in the save outputs list and if there are missing signals a warning message has to be provided, and the user has to add the signals manually. BR, Marcel

I can get spice net list from RTL. How do a get a spice netlist into Cadence composer ?

Yea, perhaps my "lousy" comment about the default colors was a tad harsh (apologies). I'll take your advice regarding dealing with the line thickness. Thanks Andrew.

Hello friends: I need to replace an obsolete MCU on an existing functional board. The old MCU is 100-TQFP, the new MCU is 128-TQFP. In addition, need to add one IC along with the new MCU. I plan to update the existing BRD file to fit the changes. What would be the best way to implement the changes, please? How to Syncing the dsn to BRD? Please recommend me the road map, along with detail step, please, use OrCAD PCB Designer 17.2

No worries. One man's "lousy" is another man's "fabulous" ;-) Andrew.

Hmm. You post a question on a 6 year old thread (suggest you read the forum guidelines ), but what's stranger is that the post you replied to actually answered your question...

I thought things were going well, until it happened again today. Along the lines of Paul's suggestion, I'm now trying with autosave 'on'. See if that has any effect. Up for any other suggestions too.

The only company I know that take a netlist and make is schematic is SpiceVision from Germany. (www.concept.de) I was hoping Cadence had a tool for this.

Hi Andrew, I was wondering if we can get end point fit with the same code.. probably with some minor modifications. Thanks, vamshiky

hello exports, starting to have longer and longer time simulation but the waveform database apparently eating up the disk space quickly for day-long simulation. how can I config the ocean script based simulation not to save any (or just by specific picked nodes. it still saves database even I'm not using save or saveOption) ? I know -nograph would not bring up any display but I think that's not avoiding to dump huge waveform dump. in IC617 thanks, David

Well, whilst SpiceVision does a very good job, as I've said more than once in this thread, Cadence does have a tool for this. File->Import->SPICE. Not quite sure why you've ignored my answer in the post you originally replied to.

I've tried openResults() and it works perfectly Thank you so much for your help. I've been working on this for weeks, and it will reduce the script length by a lot.

So you just want a line between the first and last points? That would be very easy (although it wouldn't need any of the existing best fit code because it's much simpler). Before I show you how, I want to make sure I've understood that this is what you meant... Regards, Andrew.

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