Thank you Andrew! That answers my question. I also got the same error as you, I just posted a different error accidentally. Regards, Namit
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Forum Post: RE: Changing a dynamic parameter set in tran and using design variables.
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Forum Post: RE: Verilog-A code for ADC
Hii, I am also not familiar with VerilogA. So can anyone tell me which type of ADC the above code implements? Is it pipelined ADC?
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Forum Post: RE: How to pass desVar using include file in ocean runs
Hi Andrew, Thank you for your response. Correcting the paths I used! path( " " ) definitionFile( " ") Examples of entries in design_variables.scs file are below. simulator lang=spectre desVar( "vdd" 1.2) desVar( "vddio" 1.8) desVar( "vVDD" "vdd") In the first case, ocean gives out these errors.. ERROR (SFE-1997): "input.scs" 5531: I78: parameter `Von': Cannot run the simulation because an unknown parameter `vVDD' has been specified in expression `vVDD'. Correct the expression and rerun the simulation. etc.. In the second case, ocean run gives out these errors.. ERROR (SFE-709): "absolute_path_to_file_containing_variables" 6: No master specified for instance `desVar'. ERROR (SFE-874): "absolute_path_to_file_containing_variables" 6: 10: Unexpected quoted string ""vdd". Expected end of file or end of line. Cannot run the simulation because of syntax error. Correct the error and rerun the simulation. etc... Please let me know if you need any other information. Thank you, Prasad
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Forum Post: RE: Generating Gerber RS274X In 2:3 Format & Gerber File Syntax Issue.
The correct setting for outputting artwork will need to be 3:4 if your design parameters are set to Mils accuracy 0. Not 2:3. My explanation--- 1mil =.001 10Mils =.010in 100Mils =.100in 1000mils = 1.000in 10000mils=10.000in Please note the how many numbers are before and after the decimal for 10.000 in. There are 2 leading and 3 trailing. Thus, the artwork output needs 3:4 to cover all graphics in your design up to 99 inches. And down to 1mil. If you set your accuracy down to 1. Then you need 3:5 to cover .0001 in. I hope this makes sense to you.
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Forum Post: RE: Capture CIS ORCIS-6182 I am not sure what this means
Ok, I'm having the same problem. Interestingly, its working with my CIS capacitor table, but not Inductors. Does anyone know what the character limit needs to be? MCM_C_100nF_GRM033C81E104KE14 works great. MCM_L_1nH_LQW15CA1R0K00 fails with ORCIS-6182. But, I can "view database part" with green across the board. Anyone know what the length limit is supposed to be?
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Forum Post: RE: Board Geometry OUTLINE subclass warning
John, You can still build an outline the way you want per the supplier on the BOARD GEOMETRY/OUTLINE layer. However, the outline needs to be a line not a shape. The DESIGN_OUTLINE is for a shape ONLY. That's why you cant change it's width. you can only reshape it.
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Forum Post: RE: 3D Canvas Export
Emmett, There are option switches that control the output results. In the 3D viewer- Go to Setup at the top of your screen. Setup/Preferences/Symbol representation. Select Only the Step Model button prior exporting your PDF. Cheers
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Forum Post: RE: Measurement of ground bounce and impedance of RLC network
Mr. Andrew Beckett can you please take a look into my question? Thank you for your time.
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Forum Post: 의정부회계학원ＪＲ.ｅｚＥｎＡｃ.Ｃｏ.Ｋｒ이젠아카데미 ₯의정부전산세무학원 의정부포토샵
의정부회계학원ＪＲ.ｅｚＥｎＡｃ.Ｃｏ.Ｋｒ이젠아카데미 ₯의정부전산세무학원 의정부포토샵
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Forum Post: 의정부웹디자인 ₯이젠아카데미 Jr.ᴇᴢEɴAᴄ.Cᴏ.Kʀ 의정부국비교육 의정부전산세무학원
의정부웹디자인 ₯이젠아카데미 Jr.ᴇᴢEɴAᴄ.Cᴏ.Kʀ 의정부국비교육 의정부전산세무학원
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Forum Post: 이젠아카데미をJr닷ezenac닷co.KRぉ의정부국비 의정부국비지원ぉ의정부엑셀학원
이젠아카데미をJr닷ezenac닷co.KRぉ의정부국비 의정부국비지원ぉ의정부엑셀학원
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Forum Post: 의정부고용지원센터〔... 이젠아카데미が의정부국비シ의정부국비교육
의정부고용지원센터〔... 이젠아카데미が의정부국비シ의정부국비교육
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Forum Post: RE: Verilog-A code for ADC
It's actually an algorithmic ADC (as you can see, it find the residue after each bit, doubles it and then converts that to find the next bit). However, it's not really modelling a algorithmic or pipelined converter because there's no delay in conversion - the output appears in the same cycle that the input was sampled at. The internal loop is effectively implemented as an instantaneous algorithmic converter though. Andrew.
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Forum Post: RE: How to pass desVar using include file in ocean runs
Hi Prasad, OK, in that case it's hardly surprising it doesn't work. You've put desVar function calls (which are OCEAN/SKILL functions) into a spectre syntax file. You either need to use the approach you've used and put instead: simulator lang=spectre parameters vdd=1.2 vddio=1.8 vVDD=vdd or simpler still, I'd create a file, commonVars.ocn which contains: desVar( "vdd" 1.2) desVar( "vddio" 1.8) desVar( "vVDD" "vdd") and then rather than using path/definitionFile, simply in your OCEAN script use: load("/path/to/commonVars.ocn") at the appropriate point in your OCEAN script (i.e. after the design() and before the run() somewhere). If you prefer the syntax, you can use: include("/path/to/commonVars.ocn") Regards, Andrew.
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Forum Post: Why does integrated tdnoise grow without bounds?
Hello, I have an integrator circuit that is reset periodically. Right before the reset, a sample is taken on which I would like to calculate the noise. Conceptually, after the reset, the system is not in steady state and the output (noise) variance will grow until the system reaches steady-state. The noise analysis gives me the steady state result. The output noise is attached at the end and the total integrated noise is 125uVrms. Now I run pss+pnoise with tdnoise and plot the total integrated noise vs. time. This is what the outcome looks like: Except for the y-axis scaling exactly as expected! The waveform of the reset signal is clearly visible: The system is reset between about 0 and 70ns, then the integrator starts and the total noise increases. It reaches a maximum at 250ns=0ns; then it is reset again. However, this shows the plot for different values of "Integration Stop Frequency". 4MHz, 1PHz, 10PHz, 100PHz, 1000PHz: Dependening on which value I choose for the stop frequency I can make the total noise shift arbitrarily. This does not make sense to me. For noise it's clearly visible that the system is bandlimited so the total noise must converge to a fixed number. Furthermore, it must be always smaller than the value in steady state (125uVrms from .noise). Particularly, when I make the number of sidebands (and maxacfreq in pss) very high, the number must converge to the one from .noise. Why is this? Are my settings wrong? I use pss; beat freq=4MHz, number harmonics=49, moderate, maxacfreq=1G pnoise: Start: 1, Stop: 100G (some very high number), 10pts per decade. Maximum sidebands: 51. Finally I use ADE L -> Direct Plot -> tdnoise -> Integ Output Noise, Total Noise, Start Frequency 1 Hz and Stop Frequency I vary from 1 MHz .... 10000PHz with difference results (as above). As can be inferred from the plots, the control signals run at 4 MHz with ~21:6 duty cycle. PS: This is the .noise output. Total integrated: 125uVrms.
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Forum Post: RE: Schematic Layout Synchronization
I guess what you mean is to get real time LVS funciton, like you click one part on the schematic/layout, the counter part highlighted in the layout/schematic. I am not sure if this function is integrated in Allegro, from their poster, link below, it seems the function is available, but we have not found any clue to run it. https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ic-package-design-analysis/sip-digital-design-ds.pdf
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Forum Post: set_multicycle_path using clock enable signals
Hello! For synthesis with Genus 17.1 I want to constrain a multi-cycle path inside one single clock domain from some flipflops using one clock enable signal to some other flipflops using a different clock enable signal. There is a solution for Altera Quartus , which works fine for Quartus, but not for Genus. After adapting the syntax of the Quartus solution I tried in Genus: set_multicycle_path 4 -from [get_fanout [get_pins my_component/my_clock_enable_1_reg/q]] -to [get_fanout [get_pins my_component/my_clock_enable_2_reg/q]] -setup but the command gives a list, which includes objects, which are not supported by . Here is the relevant part of the error message: Error : A given object is not suitable for this exception. [SDC-211] [set_multicycle_path] : The 'set_multicycle_path' command does not allow '-from' specifications for pins on unmapped combinational or hierachical instances ... The used clock-enable signals are used inside clocked processes as combinational logic and together with other combinational conditions the synthesis tool recognizes this as clock-enable. Here is the pseudo-code: elsif rising_edge(clk) then if (clock_enable_1='1' AND other_condition='1') then Ralf
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Forum Post: RE: Why does integrated tdnoise grow without bounds?
When you use the "time domain" noise feature of pnoise (or the "PM" jitter mode; both are now called "jitter (sampled)" in the latest versions), the simulator inserts an ideal sampler at the output of the circuit which samples the circuit at a specific instant in time during the period (it may sample at multiple times, each is a "time event"). Anyway, this ideal sampler is operating at the PSS fundamental frequency, so that means that if you sweep beyond half the PSS fundamental in the pnoise analysis, you are causing the sampler to alias the noise and so it will double count, triple count etc the noise. Because of the ideal sampler, you are capturing all the noise because it folds the noise itself into the band up to half the PSS fundamental. So do not sweep beyond the PSS fundamental frequency divided by two. Similarly do not integrate the noise beyond PSSfund/2 for the same reason. Regards, Andrew.
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Forum Post: RE: Remove /* this is a comment line */ from a file
Andrew, pcreCompile() takes an optional second argument to define all kinds of options - those options in turn need to be generated with pcreGenCompileOptBits(..) So to turn on non-greedy matching you need to go like that: (pcreCompile (pcreGenCompileOptBits ?ungreedy t )) Max
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Forum Post: Finding and counting duplicates in a list
Hi Team, If my list had ("a" "b" "c" "a" "d" "f" "a" "c" "b"), then it should give a=3,b=2,c=2. No need to give 'd' and 'f'. How to code in Cadence SKILL to find the duplicates count?
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