Thanks. I figured out a solution which I'm adding in case others find this thread in a search (or I find it in a few years). 1) As Andrew mentioned, "techGetPurposeNum" is what should have been in the original post, not "techGetPurposeName", the original was a typo. 2) shape~>lpp will return strings if the layer number and purpose numbers are defined in the tech file and numbers otherwise. Same for shape~>purpose So I can do something like this: purpose_num = if(stringp(shape~>purpose) techGetPurposeNum(tech shape~>purpose) shape~>purpose) 3) It appears that when setting ~>lpp I can use strings *or* numbers. So for example (using made up numbers and names) either of these will work. shape~>lpp = list(50 -1) shape~>lpp = list("METAL1" "drawing") And assuming layer 50 is METAL1, purpose -1 is drawing, if I set via numbers, and then access shape~>lpp I'll see the strings. That helps in terms of removing one additional layer of mapping.
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Forum Post: RE: layout object purpose number directly?
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Forum Post: Vector files and verilog ams modules
I have made a verilogams module for a 2 to 4 decoder where both the input and output buses are logic disciplines. I then made a test bench for the module which consisted of a verilog a model of a counter some vpulse sources and it was working. I was wondering if a verilog ams module can use a vector file as a stimulus with connectlib files selected to determine the logic levels. So far it doesn't seem to be working. Can vec files only work with actual device circuit models or do they work with functional and verilog ams cell views. I am attaching a picture of the test b nch with the module and the vector file, so that if I made a mistake, someone here can catch it.
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Forum Post: RE: Vector files and verilog ams modules
sorry mods can move this post to the Mixed Signal design forum. thanks
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Forum Post: RE: how to hide "DO NOT INSTALL" components
You can set "Part not Present" color to match the background when you view the schematic in variant view mode.
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Forum Post: RE: APS/Spectre simulation data too big
thx!
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Forum Post: net, terminal, signal
Hi, I'd like to change label names including pin names after selecting labels and pins that I want to change. A skill code changing text is done but I should add more lines to change pin names as well because we are using layout XL. I started to think what affects connectivity of layout XL, terminal name or pin name or net name and I'm not sure but I thought terminal name could. Now I am having trouble to change terminal name of pin and I am confused about net, terminal and signal. I have seen net and signal and terminal while writing skill codes but I don't have confidence on these. 1) If I am right that terminal name affects connectivity of layout XL, how can I change terminal name? The way I am approaching is like this below. foreach(sel selectedSet() if(sel~>objType =="rect" then t_netName = sel~>net~>name d_termID = dbFindTermByName(cv t_netName) . . d_termID~>name = t_changed );foreach 2) Can you explain what's the difference of net, terminal and signal? Thanks, Jungyoon
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Forum Post: Find Window can't pop up in OrCAD Capture 16.6
Hi, I can't find my "Find Window" when searching something. I have the "Find" icon (like telescope) in toolbar, and I can do "search" function. But, OrCAD didn't pop up Find Window to list the results anymore. (Please refer to Find Window.png) I'm looking forward to your comment. Thanks a lot. (OrCAD version is 16.6)
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Forum Post: RE: Find Window can't pop up in OrCAD Capture 16.6
HI Iting, Please try deleting capture workspace using registry editor and let me know how it goes?
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Forum Post: RE: Find Window can't pop up in OrCAD Capture 16.6
Hi rads, It works!!! Thank you very much.
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Forum Post: EM/IR Analysis Setup missing from ADE L menu
I'm trying to start EMIR analysis by looking at the example that's in: /tools/spectre/examples/EMIR_workshop/mmsim141_emir_workshop/ade_mmsim_voltus_workshop However, I found that EM/IR Analysis Setup is missing from ADE L menu. Therefore, I can't go further on GUI based EMIR flow. I've already checked the followings: 1) Successfully I've completed text based EM/IR flow workshop which is in /tools/spectre/examples/EMIR_workshop/mmsim141_emir_workshop/textonly_workshop . Thus, I believe my modification on the environment variable such as MMSIMHOME and CDSHOME is correct. 2) As default, there is a description "setenv MMSIM_ADE_EMIR true" in the file, setup_ade_mmsim_voltus.csh. It seems that this description is for setting EM/IR Analysis in ADE L to be enable. Can anyone please help me with this situation? I'd like to visualize IR drop easily via GUI based EMIR flow rather than text based EMIR flow...
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Forum Post: overlaping due to transition function verilogA
I have 3 ideal interleaving clock signals (zero rise and fall time, no delay) that have no overlaping. However, after passing through the transition function in verilogA, they overlap each other at rise and fall time durations. Does anyone have any idea to solve this problem by changing the verilogA code? y1, y2, y3: 3 ideal interleaving clock signals V(S4) <+ transition(y1,tdelay,trf); V(S5) <+ transition(y2,tdelay,trf); V(S6) <+ transition(y3,tdelay,trf);
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Forum Post: Assura QRC - Extracted View Error [ LBRCXM-644 ]
Hello, While I was trying to make an extracted view, QRC gave me the error as below: Cadence Quantus QRC Extraction - 64-bit Parasitic Extractor - Version 15.1.1-s174 Tue Jul 7 21:42:47 PDT 2015 ------------------------------------------------------------------------------------------------------------------- Copyright 2015 Cadence Design Systems, Inc. INFO (EXTQRCXOPT-243) : For Assura inputs, if the "output_setup -directory_name" option was not specified, it is automatically set to the input directory. INFO (LBRCXU-108): Starting /cds/ASSURA414/tools.lnx86/assura/bin/rcxToDfII /home/nokta/work/cad/LVS6/invLVS/__qrc.rcx_cmd -t -f /home/nokta/work/cad/LVS6/invLVS/extview.tmp -w /home/nokta/work/cad/LVS6/invLVS WARNING (LBRCXU-172): m2write fd 10, 1 tries, bytes -1 of 27, errno 9 Bad file descriptor Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.05s. @(#)$CDS: rcxToDfII_64 version av4.1:Production:dfII6.1.5-64b:IC6.1.5-64b.500.17 08/31/2015 04:54 (sjfql463) $ sub-version 4.1_USR4_HF25, integ signature 2015-08-28-0751 run on XXX.tr from /cds/ASSURA414/tools.lnx86/assura/bin/64bit/rcxToDfII on Wed Jul 18 19:49:42 2018 Loading tech rule set file : /home/nokta/work/cad/umc13nm/umc13mmrf/techRuleSets Loading umc13mmrf/libInit.il ... Loading umc13mmrf/loadCxt.ile ... done! Loading context 'umc13mmrf' from library 'umc13mmrf' ... done! Loading context 'pdkUtils' from library 'umc13mmrf' ... done! Loading context 'Util' from library 'umc13mmrf' ... done! Loading context 'userUtil' from library 'umc13mmrf' ... done! Loading context 'oxf_cb' from library 'umc13mmrf' ... done! Loading umc13mmrf/libInitCustomExit.il ... done! Loaded umc13mmrf/libInit.il successfully! *WARNING* No library model for device "RSNWELL". INFO (LBRCXU-114): Finished /cds/ASSURA414/tools.lnx86/assura/bin/rcxToDfII INFO (LBRCXU-108): Starting /cds/ASSURA414/tools.lnx86/assura/bin/avRCXxref /home/nokta/work/cad/LVS6/invLVS/__qrc.rcx_cmd -useRunName @(#)$CDS: avRCXxref_64 version av4.1:Production:dfII6.1.5-64b:IC6.1.5-64b.500.17 08/31/2015 04:50 (sjfql463) $ sub-version 4.1_USR4_HF25, integ signature 2015-08-28-0751 run on XXX.edu.tr at Wed Jul 18 19:49:43 2018 Reading rsf INFO (LBRCXU-114): Finished /cds/ASSURA414/tools.lnx86/assura/bin/avRCXxref INFO (LBRCXM-642): Constructing the RCX run script /cds/EXT151/tools.lnx86/extraction/bin/64bit//capgen: error while loading shared libraries: libtermcap.so.2: cannot open shared object file: No such file or directory INFO (RCXSPIC-27150): The following forked command failed. Contact Cadence Customer Support for assistance. /cds/EXT151/tools.lnx86/extraction/bin/64bit//capgen -techdir /home/nokta/work/cad/umc13nm/umc13mmrf/LPE -lvs /home/nokta/work/cad/LVS6/invLVS.xcn -p2lvs /home/nokta/work/cad/umc13nm/umc13mmrf/LPE/p2lvsfile -reseqn -sw3d -length_units meters -blocking RFSYMBOL,DIFF_diel,PSD_C,PLY_C,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C,MMCBP_C,MMCTP_C -res_blocking RFSYMBOL,ply,ME1,ME2,ME3,ME4,ME5,ME6,ME7,ME8,MMCBP,MMCTP -p PLY_C,Allgates,PSD_C -cap_unit 1 -blocking CMMC,MMCBP_C,MMCTP_C -blocking MOMVP1_MM_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP1_MM_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP2_MM_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP2_MM_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_SY_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_SY_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_ASY_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_ASY_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C /home/nokta/work/cad/LVS6/invLVS Forking: /cds/EXT151/tools.lnx86/extraction/bin/64bit//capgen -techdir /home/nokta/work/cad/umc13nm/umc13mmrf/LPE -lvs /home/nokta/work/cad/LVS6/invLVS.xcn -p2lvs /home/nokta/work/cad/umc13nm/umc13mmrf/LPE/p2lvsfile -reseqn -sw3d -length_units meters -blocking RFSYMBOL,DIFF_diel,PSD_C,PLY_C,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C,MMCBP_C,MMCTP_C -res_blocking RFSYMBOL,ply,ME1,ME2,ME3,ME4,ME5,ME6,ME7,ME8,MMCBP,MMCTP -p PLY_C,Allgates,PSD_C -cap_unit 1 -blocking CMMC,MMCBP_C,MMCTP_C -blocking MOMVP1_MM_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP1_MM_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP2_MM_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP2_MM_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_SY_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_SY_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_ASY_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_ASY_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C /home/nokta/work/cad/LVS6/invLVS ERROR (LBRCXM-644): Bad return status from RCX script generator. 0x100 INFO (LBRCXM-709): ***** Quantus QRC terminated abnormally ***** Also, I checked CIW but there was no addtional error. Do you have any suggestion about it?
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Forum Post: how to automatically select the content of a field when a form appears?
Hi all, I have create a form using hiCreateAppForm(), and when the form was invoked, the cursor will automatically focus on the first editable field, but will not select the content of that field. I want to make the select automatically, so I can change the content directly by using keyboard. Is there any ways to implement it? Another question: Is there any ways to remove the “Help” button from the form? Regards, Dave
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Forum Post: How to use symbols (units) in string?
Dear Cadence Community, I have a small query. How can we use unit symbols while printing a certain string? e.g. 1k Ω . How can i add this Ω symbol for Ohm in the string? Also, how to add subscripts and superscripts to it? e.g Ω^-1 for 1/Ω Regards, Haris
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Forum Post: RE: net, terminal, signal
Hi Jungyoon, A terminal is always on a net (or "has" a net) but not vice versa. Internal nets do not have a terminal attached - meaning you cannot connect to them from outside. So net~>term returns nil for internal and a terminal OA object for external nets. If a shape (for example a rectangle) is a pin you get at the corresponding terminal like this: rect~>pin~>term ...so to rename the terminal: rect~>pin~>term~>name= I'am not sure about the signal though... Max
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Forum Post: RE: net, terminal, signal
oh - and changing the terminal name changes the associated label name accordingly...
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Forum Post: RE: How to use symbols (units) in string?
Hi Haris, You can't. Virtuoso has primarily 7-bit ASCII support, with some limited 8-bit ASCII support. For characters with an ASCII code above decimal 127 (177 in Octal) as on this page , you can use (for example); printf("Fraction \276\n") will output: Fraction ¾ However, characters like the Greek Omega symbol is not possible - that would require Unicode support, which is not available throughout Virtuoso. Regards, Andrew.
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Forum Post: RE: overlaping due to transition function verilogA
I think you'll need to describe how you're creating y1,y2 and y3. Ideally a picture of the waveforms (y1,y2,y3 and S4,S5,S6) would help. Andrew
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Forum Post: RE: How to use symbols (units) in string?
Hi Andrew, Thankyou for your detailed response. Much appreciated. Regards, Haris
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Forum Post: RE: how to automatically select the content of a field when a form appears?
I think if you just set the field with hiSetCurrentField: hiSetCurrentField(myform 'f1) Then it makes that the focus field, but also selects the content when it's displayed. Just to double check, which IC subversion are you using (Help->About in the CIW will tell you)? Regards, Andrew.
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