Hi, There is a Rapid Adoption Kit (RAK) on Voltus-Fi EMIR flow which will take you through the GUI based flow. If you didn't find the EMIR form in ADE, it means you are on an old IC version. Can you confirm which versions of IC and MMSIM are you using? Here's the pointer to the RAK: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od00000066MmTEAU&pageName=ArticleContent&sq=005d0000001T4VEAA0_201871911433325 Regards, Saloni
↧
Forum Post: RE: EM/IR Analysis Setup missing from ADE L menu
↧
Forum Post: RE: overlaping due to transition function verilogA
Here is y1, y2, y3 waveforms. Of I pass them through the transition function as above with tdelay =0 and trf = 1p then they will create rise and fall time.
↧
↧
Forum Post: RE: overlaping due to transition function verilogA
As already asked for, can you share waveforms for S4, S5 and S6 also?
↧
Forum Post: RE: overlaping due to transition function verilogA
Because it is not available now. I will send it later. However, from these signals it is easy to see how S4, S5, S6 can be overlaped when passing through the transition function.
↧
Forum Post: RE: EM/IR Analysis Setup missing from ADE L menu
Hi, The versions I use are as follows. IC06.16.005 MMSIM14.10.896 Are they too old to use the EMIR form in ADE? Regards, yyama
↧
↧
Forum Post: RE: EM/IR Analysis Setup missing from ADE L menu
Hi, I can see the EMIR form in ADE with IC6.1.6-64b.500.7, but not with IC6.1.6-64b.500.3. I don't have all intermediate releases available to test I'm afraid, but it seems you are using a release very close but before the form was made available. IC616 is in general quite old now, can you move to IC617? Regards, Saloni
↧
Forum Post: RE: overlaping due to transition function verilogA
Well, you either need to arrange the input data to transition to have at least 1ps gap between the edges so that they don't overlap after the transition, or another possibility would be to have: V(S4) <+ transition(y1,tdelay1,trf); V(S5) <+ transition(y2,tdelay2,trf); V(S6) <+ transition(y3,tdelay3,trf); (i.e. separate delay variables for each transition), and then set each of tdelay1, tdelay2, tdelay3 to be (at least) 1ps when y1, y2, y3 (respective) goes from 0 to 1, and for these variables to be 0 (so no delay) when each goes from 1 to 0. This will introduce a 1ps delay on the rising edges, which means it would avoid the falling edge of the other signals. I did think about putting together an example, but I think the explanation above should be clear enough, and any example Saloni or I create wouldn't necessarily match how you're generating y1, y2, y3 anyway. Oh, why not - here's the code (it only took me 5 minutes): `include "disciplines.vams" module nonoverlap (s4,s5,s6); output s4,s5,s6; electrical s4,s5,s6; parameter real clock=50p; parameter real trf=1p; real tdelay1=0; real tdelay2=0; real tdelay3=0; integer y1,y2,y3; integer cycle; analog begin @(timer(0,clock)) begin cycle=cycle+1; if(cycle%3==0) begin y1=1; tdelay1=trf; end else begin y1=0; tdelay1=0; end if(cycle%3==1) begin y2=1; tdelay2=trf; end else begin y2=0; tdelay2=0; end if(cycle%3==2) begin y3=1; tdelay3=trf; end else begin y3=0; tdelay3=0; end end V(s4) <+ transition(y1,tdelay1,trf); V(s5) <+ transition(y2,tdelay2,trf); V(s6) <+ transition(y3,tdelay3,trf); end endmodule Here's the graph - note I increased the rise/fall time to make it a bit more obvious: Regards, Andrew.
↧
Forum Post: RE: Assura QRC - Extracted View Error [ LBRCXM-644 ]
Hi, I once had a similar error. The solution I found here worked for me. Kind regards, Matthias
↧
Forum Post: RE: net, terminal, signal
Signals are scalar nets (i.e. never any more than one bit wide), and a bussed or bundled net in the database will have a number of member signals (which is as wide as the bus or bundle). However, why are you trying to change the connectivity information if you're using VLS XL - you'll presumably then make it inconsistent with the connectivity source (the schematic). Normally you'd update the schematic and then use Update Components and Nets to update the layout, which will adjust the connectivity in the database accordingly. Regards, Andrew.
↧
↧
Forum Post: RE: Vector files and verilog ams modules
I won't bother moving it - just as easy to answer here. Vector files (and VCD files) can only drive analog nets, not digital nets in a mixed-signal simulation. You'd have to stick a resistor (say) between the net being driven by the vector file and the module with logic inputs. That's because the discipline resolution is not influenced by the presence of vector files, and so it wouldn't know to add a connect module instance (an interface element) on that net. Regards, Andrew.
↧
Forum Post: RE: Cadence Virtuoso Simulink Co-simulation
Yes, that's still supported. The video talks about this being between spectre and simulink (which does also exist) but what you're actually seeing in that video is a AMS-Simulink co-simulation. I gave a presentation together with the MathWorks which covered this at CDNLive EMEA in 2016, and there's a video of the same content at https://www.cadence.com/content/cadence-www/global/en_US/home/tools/custom-ic-analog-rf-design/circuit-design/virtuoso-ade-product-suite/mathworks-integration.html (this is a longer presentation and video showing various ways the products from the two companies work together). This is in the documentation for the AMS Designer Environment - you can find it at /doc/amsdMatSim/amsdMatSim.pdf Regards, Andrew.
↧
Forum Post: RE: EM/IR Analysis Setup missing from ADE L menu
Actually, Andrew just checked that EMIR form was introduced in IC6.1.6-64b.500.7. But I will suggest you move to the latest IC and Spectre (MMSIM) versions if possible to be able to access all new EMIR flow features (and avoid issues that may have existed earlier). Regards, Saloni
↧
Forum Post: RE: overlaping due to transition function verilogA
Here's a more concise version of the model above, just because I thought it was a bit verbose. Essentially does the same thing though: `include "disciplines.vams" module nonoverlap (s4,s5,s6); output s4,s5,s6; electrical s4,s5,s6; parameter real clock=50p; parameter real trf=1p; real tdelay1=0; real tdelay2=0; real tdelay3=0; integer y1,y2,y3; integer cycle; analog begin @(timer(0,clock)) begin cycle=cycle+1; tdelay1=trf*(cycle%3==0); y1=(cycle%3==0); tdelay2=trf*(cycle%3==1); y2=(cycle%3==1); tdelay3=trf*(cycle%3==2); y3=(cycle%3==2); end V(s4) <+ transition(y1,tdelay1,trf); V(s5) <+ transition(y2,tdelay2,trf); V(s6) <+ transition(y3,tdelay3,trf); end endmodule Andrew
↧
↧
Forum Post: RE: how to display refdes rats on manufacturing-assembly drawing
Enable the user preference under Placement - General called display_refdes_rats then this are shown as part of the Refdes\Assembly_top layer so make sure that is turned on.
↧
Forum Post: RE: Unable to import psm path
So the padstack has a shape symbol as part of it and PCB Editor cannot see that file. Make sure that any filename.dra and filename.ssm are available in your psmpath. Personally I tend to keep dra and associated ?sm (psm, bsm, ssm, fsm, osm) in the same folder. There's a guide to setup psmpath and padpath orcad.co.uk/.../Defining_padpath_psmpath.pdf
↧
Forum Post: How to start multithread
I am building a skill which perform a heavy calculation. Does any body know how to start multithread to calculate parallel. Just like running DRC in allegro. Seems it start multithread to run the DRC
↧
Forum Post: RE: Vector files and verilog ams modules
Thanks, Andrew for the quick response. Is the discipline resolution influenced by the presence of verilog A models and analog sources like a pwl source? If I use a connect module instance and just drive the decoder (with logic inputs) with just a voltage pwl source would that work? Thanks for the help.
↧
↧
Forum Post: RE: how to automatically select the content of a field when a form appears?
Thanks Andrew, I’m using the IC617isr15, And I have tried the function hiSetCurrentField(), but it seems doesn’t work well at all times . Below is my major script, could you please help me to find the problem, thanks! procedure(myDisplayForm() one = hiCreateIntField(?name ‘one ?prompt “test number” ?value 1) ;two = ... hiCreateAppForm(?name ‘myForm ?prompt “My Form” ?fields list(one) ?button ‘OKCancel) hiDisplayForm(myForm) hiSetCurrentField(myForm ‘one) ) Type in myDisplayForm() in CIW. Regards, Dave
↧
Forum Post: RE: how to automatically select the content of a field when a form appears?
The code didn't quite work because the arguments to hiCreateAppForm are incorrect. I tried a number of things, and I think you can't do it when the form is created. You can however do it on subsequent calls to hiDisplayForm - so if you're displaying an existing form which is not being recreated. I tried using hiInstantiateForm beforehand, setting hiSetCurrentField before displaying the form (it makes no sense to do it after the display as you have, since hiDisplayForm will block by default). I even tried enqueueing the commands and adding a display, cancel and re-display to see if that helped (it didn't). procedure(myDisplayForm() one = hiCreateIntField(?name 'one ?prompt "test number" ?value 1) ;two = ... hiCreateAppForm(?name 'myForm ?formTitle "My Form" ?fields list(one) ?buttonLayout 'OKCancel) hiSetCurrentField(myForm 'one) hiEnqueueCmd("hiDisplayForm(myForm)") hiEnqueueCmd("hiFormCancel(myForm)") hiEnqueueCmd("hiDisplayForm(myForm)") ) So you probably will need to contact customer support and ask for an enhancement to support this. On subsequent calls, I can just do: hiSetCurrentField(myForm 'one) hiDisplayForm(myForm) and then it seems to work (actually the set current field isn't really needed, since I only have one field). I didn't answer your other question in your original post about not having the Help button. I don't think you can remove it, but you could add: ?buttonDisabled list('Help)) to the hiCreateAppForm call. This will at least grey out the Help button. Regards, Andrew.
↧
Forum Post: Uncheck update instances in rename cell dialog
Is there a way to uncheck the Update Instances box in Rename Cell dialog by default (eg. in .cdsinit)?
↧