Thanks Max, I understand a terminal can be a port of schematic having a net and being not an internal net. Am I understanding in the right way?
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Forum Post: RE: net, terminal, signal
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Forum Post: RE: net, terminal, signal
Thanks Andrew for explaining what signals are. I had hard time when I should edit tons of net names like nets A by hand due to schematic change. So I wrote a skill code editing label's names at a sitting. I rarely use Layout XL but many use Layout XL here so I felt I have to add more codes to editing pin names as well. Please give me some advice if you have another good idea for this issue, Andrew. Thanks, Jungyoon
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Forum Post: RE: Unable to import psm path
Thanks Steve I tried putting the dra, psm, and pad into the same folder perfectly flat, but after exporting it still puts an error and when placing the symbol in Allegro 17.2. Is there a file other than psm in a psm path, pad in a pad path?
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Forum Post: Multiple flight wires to symbol terminal
While placing more than a single flight wire on a terminal in layout, moving the instance will cause the flight lines to remain in the same place, but the connected terminal will create a wire going back to the original location. If doing this with a single flight wire, this is not the case and the flight wire will follow the terminal. Is there a way to have multiple flight wires do the same thing as a single flight wire?
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Forum Post: RE: EM/IR Analysis Setup missing from ADE L menu
Hi, Thank you very much for your help. I will move to the latest IC and Spectore(MMSIM) so that I will be able to see the EMIR from in ADE. Regards, yyama
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Forum Post: RE: Vector files and verilog ams modules
I was playing around with it a bit more. Will it work if I attach resistors at the input and output buses like below? I am attaching my vector file as well. The waveforms I get are wrong. The inputs don't seem to change after every 10ns but seem to stay the same for the entire length of the simulation (0,0). I get the right output but was wondering why the inputs don't change.
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Forum Post: Simulating *.vams generated from ADE-L in DoT flow
Hi All, Wondering, whether it is possible to simulate a *.vams generated from ADE-L (using AMS + ultrasim) in DoT flow? To explain, I have a schematic which has both digital and analog components, so I had to use AMS for netlisting. Now since my design is complex block, i Would like to use verilog testbench to reduce testbench development time, for each case. Is it possible to do? any hints? if not, could anyone suggest me any better way to use script based testbench. Initially I was using VCD for doing the same, VCD has no issues with pure analog simulation. But When I change my simulator to AMS, the signals that are represented by bus (e.g: S ) all ends up floating nodes. I do have alias [*] setup in my vcd control file. As I wasn't able to fix it. I had to move to DoT flow and I am not sure whether it will work or not. any suggestions or ideas? Thanks! Aarthy
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Forum Post: Skill to import template default
Hello, I have a template (abc.dra) by default it has some new layers, text size & colors. While opening any footprint this template need to import automatically. Please help. Thanks in advance.
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Forum Post: RE: Uncheck update instances in rename cell dialog
You can put the following entry in your ~/.cdsenv file: cdsLibManager.rename updateOn boolean nil Note that putting an equivalent envSetVal call in your .cdsinit won't help, because the library manager is a separate process that doesn't read the .cdsinit. So this ideally needs to be in a .cdsenv file which by default looks in your home directory (not working dir). However, it's possible by various methods (either the $CDS_LOAD_ENV Unix env var or using the csfLookupConfig file mechanism) to look for it elsewhere. You could also put: envSetVal("cdsLibManager.rename" "updateOn" 'boolean nil) into a cdsLibMgr.il file which is found via the Cadence Search File (setup.loc) mechanism - so probably in your home or working dir. Regards, Andrew.
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Forum Post: RE: net, terminal, signal
The best thing would be for you to contact customer support - it's still unclear to me why you need to do this or precisely what it is you're trying to change. I could easily end up writing a whole load of code which is completely unnecessary because I didn't know what you're trying to do. If you're using Layout XL (or your users are), then it's important for the layout to stay consistent with the schematic - so changing connectivity on the layout side could easily be problematic. Andrew.
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Forum Post: RE: Multiple flight wires to symbol terminal
I don't know what you're asking. What's a "flight wire"? The post title talks about symbols but your post text talks about layout - it's unclear what you mean. Perhaps posting some pictures would make it clearer what you're talking about, because currently I have no idea! Regards, Andrew.
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Forum Post: RE: Vector files and verilog ams modules
In the AMS log file, you'll have seen something like: Notice from spectre during topology check. Only one connection to the following 2 nodes: in in You need to use vname in[0] in[1] instead (i.e. square brackets) - then it would have worked. Andrew.
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Forum Post: RE: Vector files and verilog ams modules
Oh, and by the way, it's much better if you post the contents of a text file as text rather than as a screenshot. Then it saves anyone looking at this time because they don't have to re-type the contents... Andrew.
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Forum Post: RE: Simulating *.vams generated from ADE-L in DoT flow
Aarthy, Yes, this is possible, but it's unclear what you don't know. Running AMS from the command line with a digital test bench (or doing the same from within ADE) is perfectly possible. You can use "runams" to generate the netlist of your design, and then incorporate that into a command-line "irun" (or "xrun" if using the newer Xcelium simulator). Note that if you're talking about using VCD inputs in the ADE Simulation Files form, then these can only drive analog nets (even in a mixed-signal simulation), and the names in the info file do need to match those in the netlist. Not quite sure exactly what your issue is. Maybe it would be better to contact customer support as it may need a bit of back and forth discussion to understand fully what your setup looks like and what you're trying to achieve. Thanks, Andrew.
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Forum Post: RE: how to display refdes rats on manufacturing-assembly drawing
Thanks Steve. but this is only applies to Refdes\Assembly_top. Is there also a refdes rats for variants assembly drawing?
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Forum Post: RE: Export .brd file as .alg.
There is no option in PCB editor to export to Altium. You may need to check with Altium for Import details.
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Forum Post: RE: how to automatically select the content of a field when a form appears?
Hi Andrew, Thanks a lot for your kindly response and what you did. I tried to use the subsequent calls as you said, and it works. But since I integrated the form to a pulldown menu, it meet another problem. Assuming I have opened two layout cell which named layoutA and layoutB, and launch a form in LayoutA, then I get a formA, Now launch a form in layoutB, my desire is get a formB that is different from formA, but actually the shown form is still formA. How can I get a new form for every different layout cell? Let me show you the complete code. procedure(myDisqplayForm() let((one two) one = hiCreateIntField(?name 'one ?prompt "first number" ?value 1) two = hiCreateFloatField(?name ‘two ?prompt “second number” ?value 1.5) hiCreateAppForm(?name 'myForm ?formTitle "My Form" ?fields list(one two) ?buttonLayout 'OKCancel ?callback “println(cv) printf(“%n %n\n” myForm->one->value myForm->two->value)) ?mapCB “cv=hiGetEditCellView()” ) myForm ) myDisqplayForm() hiSetCurrentField(myForm ‘one) procedure(myMenu(args) let((cw menu1) cw=hiGetCurrentWindow() menu1=hiCreateMenuItem( ?name ‘menu1 ?itemText “menu A” ?callback “ hiDisplayForm(myForm) ”) allMenuID=hiCreatePulldownMenu( ‘allMenuID “All Menu” list(menu1)) hiInsertBannerMenu(cw allMenuID 0) list(menu1) )) deRegUserTriggers(“maskLayout” nil ‘myMenu) Looking forward to your reply. Regards, Dave
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Forum Post: RE: PDF Export--> Name duplicating
Check your Artwork control form .. general parameters .. prefix section. Remove any prefix from there and Generate PDF
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Forum Post: RE: Layer Bound keeps turning back on
Remove BOUND class from the Color dialog - Visibility pane - Visibility classes and then from Layers tab uncheck the Bound class. Bound class will not be visible to select.
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Forum Post: RE: how to display refdes rats on manufacturing-assembly drawing
Not currently possible, talk to Cadence support and get an enhancement request raised.
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