I got it to work with doing a *.pad fix with the db doctor tool, the padstack were too old and couldn't be opened individually. I place and the footprints look great.
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Forum Post: RE: Symbol and layer embedding requirements do not match.
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Forum Post: RE: Unable to import psm path
I did the update to the pad stacks too and I am able to place everything in the library. thank you all for all your help.
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Forum Post: RE: Multiple flight wires to symbol terminal
Hi, Andrew, I have included a picture of what is going on. The first shows two flight lines/wires connecting to the power source V1. If we move V1 down a little bit we produce the second picture, which shows that an additional node connecting the flight lines has been created. This node is undesirable in our schematics and may produce dangerous extra connections. Is there a way to automatically redraw the connections to make them result in the final picture?
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Forum Post: Project Management Software
The company I work for does not create many designs. We do however have two seats of OrCad capture and PCB designer. Currently, designs are stashed on the network in some folder. If the PCB guy dies or quits, It'll be hard to find his design files. We make many more mechanical assemblies than electrical and use Autodesk inventor as the solid modeling and drafting software and use Autodesk Vault as the project management and revision control software. Supposedly we can stick the any file type we want into a folder in Vault, but having native support would be ideal. Does anyone know if a Vault Plugin was created for Orcad files? Or... can anyone recommend a software for managing the PCB designs and versions? I'm talking about Product Lifecycle Management software. Software that does version control, engineering change management, I do already know about OrCAD Data management. If this is what you were going to recommend, would it be overkill for just two seats of Orcad? Thanks in advance. Neil
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Forum Post: RE: Multiple flight wires to symbol terminal
I can't really see why this would cause any real problems - I can't see how it could be dangerous either. Most people wouldn't want flight lines but would prefer routed wires, but presumably you've turned that off for some (rather unusual) reason. Anyway, what you want can be done. when doing the Edit->Stretch command (usually bindkey "m"), bring up the Options form - this is usually achieved by using F3 or double-clicking the right mouse button: Ensure that the Route Method is set to "simple" (I think you must have had it set to "flight", which is not the default - "full" is the default). This will produce connections just like the third picture above. There is another way, which is to use the F4 key to toggle partial selection (also on Edit->Select->Filter and check "Area Partial Selection"), and then do an area select including the voltage source (and the end of the flight lines on the top pin of the source). However, this approach means you have to use area select to select the device, which may be less natural for you. Regards, Andrew.
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Forum Post: RE: Can I shrink an imported schematic?
Thank you for your response! It looks like changing the unit of measure would have worked, because reducing it from 0.1" to 0.025" made my existing symbols look tiny! What I ultimately did, though, was to recreate the auto-generated schematic using my own symbols and the default unit of measure.
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Forum Post: RE: Project Management Software
I don't think I would ever design without a repo to avoid losing work. Unless everything was stored on a ($$$$) NetApp server with hourly snapshots. I really like GIT. It's easy to use GitHub.coim as your repo server. But, SVN works great too. These are usually thought of as "coder" repositories. But, there's exponentially larger numbers of coders than cad designers. This means there's a number of paid and "free"(if you want to share your data with the world, like GitHub. I pay because I don't.) cloud services to use as your repo, or you can set one up for yourself. If you're new to all this, code repo systems come in two separate packages. The UI front end (I love Atlassians free SourceTree tool) usually installs or recommends a good client-side package that is the underlying mechanism. These will bring you sorrow and joy as you miraculously pull yourself from the brink of disaster (schematic changes, software issues, disk crash). Just have to understand that Forking makes life interesting (preserve your current file tree and create a separate working copy of everything with the option of merging everything back together into the main thread at some point). Anguish and sorrow can come from modifying a cad file before checking to see if anyone else made and committed their change. You are now blocked. These systems won't allow you to "commit" your changes unless you applied these edits to the latest file in the repository. If the other person is willing to trash their changes, you pull their change, then overwrite it with the renamed copy of your version of that file. Then the system will let you push or commit.
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Forum Post: RE: Verilog A to symbol
Hi, I know its against forum rules, but I think this question will make more sense here. Please excuse this time. But if I have to do monte carlo simulation in this file how should I include the cds_inherited_parameter function, should it be in all the three file for the same parameter or including cds parameter in file L1 will be sufficient? Thank you warmest regards shobhit
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Forum Post: RE: CDL import with SpiceIn: W + L wrong!
3 years after posting this question, I found myself asking it again and finding my original post. After some fumbling around, I was able to fix a CDL import scale issue with this syntax: .OPTION SCALE 1e-6 The syntax of ".SCALE METER" or ".SCALE 1e-6" caused import errors.
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Forum Post: RE: Verilog A to symbol
I would expect it would be in PCNFET rather than PCNFET_L1, but then again you didn't say what it is you're planning to statistically vary. The example (as you posted it before) had all instance parameters, whereas in this case you'd need at least one global parameter (which ends up being locally varied for mismatch) which is used within the model somewhere. See this article on how to define the parameters within a VerilogA model for Monte Carlo. Perhaps if you explained what you planned to vary, it would be easier to answer? Oh, and it would have been better to create a new thread and include a link to the original thread. This thread is already very long and so pity the poor reader who searches and finds this thread for (say) the monte carlo issue and then has to thread through the massive history above... Regards, Andrew.
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Forum Post: RE: CDL import with SpiceIn: W + L wrong!
I just did some testing with a netlist that looked like this: * .GLOBAL VDD VSS .SUBCKT myCdlInv Y A M1 Y A VDD VDD P L=6e-08 W=6.6e-07 M2 Y A VSS VSS N L=6e-08 W=3.3e-07 .ENDS myCdlInv This imports with the dimensions as specified untouched (apologies for the typo in the messages!): CDF parameter not found for 'L'. User property will be cretated Created propName='L'; propType='float'; propVal='6e-08'. CDF parameter not found for 'W'. User property will be cretated Created propName='W'; propType='float'; propVal='3.3e-07' If the netlist has the CDL directive *.SCALE (note that it has a * before it because it is not SPICE - CDL often uses a single star for such "pragma"): * .GLOBAL VDD VSS *.SCALE METER .SUBCKT myCdlInv Y A M1 Y A VDD VDD P L=6e-08 W=6.6e-07 M2 Y A VSS VSS N L=6e-08 W=3.3e-07 .ENDS myCdlInv Then they are indeed scaled: CDF parameter not found for 'L'. User property will be cretated Created propName='L'; propType='float'; propVal='0.06'. CDF parameter not found for 'W'. User property will be cretated Created propName='W'; propType='float'; propVal='0.33' If you then add: * .GLOBAL VDD VSS *.SCALE METER .OPTION SCALE 1e-6 .SUBCKT myCdlInv Y A M1 Y A VDD VDD P L=6e-08 W=6.6e-07 M2 Y A VSS VSS N L=6e-08 W=3.3e-07 .ENDS myCdlInv then that undoes the effects of the *.SCALE METER. Obviously just removing the *.SCALE METER or putting an additional * in front (so **.SCALE METER) does the same thing. Note that .SCALE METER will not work because that's not a valid CDL command - it is *.SCALE METER. So overall, my guess is that your netlist (somewhere) has a *.SCALE METER in it, and that's what was causing the original problem. Adding the .OPTION SCALE 1e-6 just reverses the effect of that. Regards, Andrew.
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Forum Post: Include CDF callback parameters in netlist
Dear All, I'm completing a test design using the gpdk045 and gm/ID methodology for educational purpose. For my technology generation (lookup tables of DC sweeps) I use the gm/ID starter kit scripts of Boris Murmann freely available on the net which I have adapted for the gdpk045. This enables quickly looking at design trade-offs in Matlab. However the results of a simple single transistor simulation between Virtuoso & Matlab are different. This is because the area & perimeter parameters are not included in my netlist, but are included in a Virtuoso simulation. For a difference in netlist see below: mn (vdn vgn 0 vbn) g45n1svt l=length*1e-6 w=5e-6 nf=5 <-- how it is scripted in Matlab netlist generation NM3 (net09 net09 0 0) g45n1svt w=(5u) l=45n nf=5 as=460f ad=460f ps=6.92u \ <-- How virtuoso simulation netlist looks like pd=6.92u nrd=18.4m nrs=18.4m sa=140n sb=140n sd=160n sca=72.26287 \ scb=0.06569 scc=0.00861 m=(1) These CDF parameters: as, ad, ps, pd, nrd, .. are calculated using callback functions which depend on the transistor dimensions. How can I use these callback functions to extend my Matlab netlist so I can achieve accurate lookup tables? Best regards
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Forum Post: RE: Create a symbol from layout
Hi Dear Andrew Due to my problem for checking LVS: I am trying to make a netlist by Virtuoso CDL Out from my schematic that includes the symbol which i have created. I have attached the CDL out template, also the output netlist file and the source.added file are in the following respectively: ************************************************************************ * auCdl Netlist: * * Library Name: mahanisi * Top Cell Name: TB_LVS * View Name: schematic * Netlisted on: Aug 2 09:28:40 2018 ************************************************************************ .INCLUDE /.../source.added *.BIPOLAR *.RESI = 2000 *.RESVAL *.CAPVAL *.DIOPERI *.DIOAREA *.EQUATION *.SCALE METER *.MEGA .PARAM ************************************************************************ * Library Name: mahanisi * Cell Name: TB_LVS * View Name: schematic ************************************************************************ .SUBCKT TB_LVS pNEG pPOS pS_NEG pS_POS *.PININFO pNEG:B pPOS:B pS_NEG:B pS_POS:B XC0 pS_POS pS_NEG pS_NEG crtmom_rf nv=288 nh=288 w=160.0n s=160.0n stm=3 spm=5 + m=1 XI13 pNEG pPOS pS_NEG pS_POS .ENDS source.added file's text is in the following: * SPICE NETLIST *************************************** .SUBCKT MN_V1_23_07_can NEG POS S_NEG S_POS .ENDS *************************************** Could you please take a look at them and investigate my problem? The problem is: When the netlist is created by CDL Out the subcircuit can not be detected, however i have added the intended subcircuit in source.added file by myself.
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Forum Post: RE: Create a symbol from layout
I have also attached the schematic for understanding the pin configuration
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Forum Post: RE: Create a symbol from layout
Two questions: What views do you have for the MoM cell (presumably called NM_V1_23_07_can)? Perhaps show the library manager contents for that cell? What does the auCdl simulation information look like in the CDF for this cell (using Tools->CDF->Edit in the CIW)? Regards, Andrew.
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Forum Post: RE: Assura selected rule checking
Hi Quek, I have the similar doubt on it. "Enable Limit DRC" can only used to limit rules based on layers.I have 200+ DRC rules and they are classified to different classes based on the priority. Suppose, I want to run a particular class of DRC rules. Is "Enable Limit DRC" can perform the same or any other way I can perform this?
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Forum Post: RE: Create a symbol from layout
1.In the first situation when i have created a symbol by Keysight Momentum-Virtuoso tool the following views are: ads auLvs layout momentum mommdl spectre symbol then i am copying the symbol view and making the auCdl then auCdl appears in the views list. 2.
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Forum Post: RE: Variants: why all attributes of a component are visible?
I found this environment variable "CDS_VARIANT_PROP_VIS" in Cadence Help and it seems the responsible of my problem (all attributes that appears in the schematic are "variant properties"). I have added this environment variable in the "Advanced system settings" (Window 7 64bit) but nothing change.... Do you know if there is something else I can do? Thanks for your help
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Forum Post: RE: Assura selected rule checking
Hi harisps Assura's "Limit DRC" function can be used to limit the number of DRC rules based on input layers, output layers, message and cmd. You can refer to $ASSURAHOME/doc/assurauser/assurauser.pdf for more details. Please kindly avoid replying to old threads. It would be best if you can start a new thread for your issue. Best regards Quek
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Forum Post: DBID of overlapping components
Hi, can you please help me with one more issue. I need to get dbids of overlapping components in design. Thank you in advance for any advice.
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