OK, you have two choices (both require you to edit the "Base" CDF (you're showing the Effective CDF above - the Base CDF is necessary if you want to save to disk and the CDL netlister to run in background which is the default): Set the netlistProcedure to ansCdlSubcktCall - in this case it will netlist with whatever the CellName is (which in your case is OK as it matches the external subckt) Set the netlistProcedure to ansCdlCompParamPrim and then set modelName to NM_V1_23_07_can (this is needed if the cell name doesn't match how you want it netlisted). The ansCdlCompPrim is not intended for netlisting instances of subckts (i.e. with the namePrefix being "X"). Regards, Andrew.
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Forum Post: RE: Create a symbol from layout
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Forum Post: RE: Is it possible show origin in Allegro
You could also go to Setup, Design Parameters, Display tab, then on the righthand side under Enhanced Display Modes, check the box next to Design Origin.
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Forum Post: RE: Include CDF callback parameters in netlist
I managed to find the kit (would have made it easier if you'd actually given a link - it's here ). The simple answer is no - since it runs completely outside Virtuoso, it wouldn't be able to see the CDF callbacks - for that a component in Virtuoso would need to be created. However, looking at what the code is doing, I don't think as, ad, ps and pd matter (since these just affect the capacitance and so don't affect the dc results) - although they are easy enough to compute given that they are just the area and perimeter of the source/drain regions. The stress parameters sa, sb and sd are unaffected by the width and length of the device - so you can find the fixed values from an experiment in Virtuoso and put them in your generated netlist. The well-proximity effect parameters sca, scb and scc are unaffected by the length (which is what the Matlab code seems to sweep) and are fixed for a specific width. From what I can see, this Matlab code generates data for a given width - so presumably you could just see what values are computed by the callbacks for that width and put them into your generated netlist. For any more than that, it would be best to contact the author of this "kit". Regards, Andrew.
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Forum Post: Mass Texting Service | TheTexting
It can support flippancy from understudies. A kindred educator I know works in a region where instructors are urged to connect with understudies on a service called Remind. Instructors convey mass texting service messages to understudies that incorporate the homework task as a connection.
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Forum Post: RE: Create a symbol from layout
The ansCdlCompParamPrim for netlistProcedure and change the model name to device name were useful for creating netlist from schematic and now the subcircuit is in schematic. Due to checking LVS when the Calibre want to compare layout vs Schematic it compares Netlist source ( the .cdl file which has been created by schematic) vs Layout source from GDSII file (which has been created as .sp file) The current problem is that the .sp file does not include the intended device. The .sp file's text is as follow: * SPICE NETLIST *************************************** .SUBCKT TB_LVS pS_NEG pS_POS pPOS pNEG ** N=4139 EP=4 IP=0 FDC=1 X0 pS_NEG pS_POS pS_NEG crtmom_rf w=1.60761e-07 s=1.59913e-07 nv=289 nh=289 stm=3 spm=5 $X=137250 $Y=-152160 $D=251 .ENDS *************************************** Could you please guide me about the mentioned matter? I will appreciate if you could inform me about how the .sp file is created from GDSII? Is there any tool setting for Layout like CDL export to could recognize the subcircuit to the translator in layout? Sincerely
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Forum Post: RE: about lines startend points
hi dave very appreciate your reply. i tried it , it cant work. it's seem as there is no children attibutes, and there is no children attibutes in line attributes shown in the image above. i tried other attributes in the line attributes table also , cant get work still. could you give me some moer advice please ? i have stucked here several days
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Forum Post: RE: Create a symbol from layout
I am assuming that this .sp file is created by Calibre LVS? If so, then you would be best asking this to Mentor, since Calibre is their tool (it's not a Cadence tool). I imagine that it's not recognising the device in the layout during the extraction part of the LVS and just sees it as routing - I mentioned this as being a likely thing you'd have to deal with in an earlier reply. Other than the generation of the CDL netlist, this is mostly an issue for Calibre, so this is not the best place to ask such a question. Andrew.
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Forum Post: Preventing a stupid schematic mistake with NMOS back-gates
I have a question that I suspect is more of a pdk thing than a Cadence thing. A regular PMOS symbol in our TSMC 0.18um library has 4 terminals (D, G. S. BG). That's fine. A regular NMOS symbol also has 4 terminals (D, G. S. BG) but that's not so fine because the BG terminal is really the substrate and there's only one place that should (normally) be connected i.e. ground. Having it available as a pin enables trouble because you can connect it to anything. Note that the library also contains isolated deep n-well NMOS devices that do have a valid BG terminal, but I'm focusing on just the regular NMOS for this discussion. In the attached diagram, I show two NMOS "diode" stacks. The left stack has all the NMOS devices having their BG terminals connected to ground. The right stack has all the NMOS devices with their BG terminals connected to their source terminals. In the real world, the BG terminals in the bad stack would short their source terminals to ground so you'd only end up with one effective diode in that stack (the top one). Some thoughts: when you do a check and save on the attached circuit you'd hope that you'd get an error for the bad stack (global substrate shorting out multiple different nets), but you don't. When you run a simulation of the circuit in Spectre it works just fine - no warnings or errors and the bad stack produces an accumulating set of Vgs voltages just like the good stack. We just had a situation where a designer who should have known better used a bad stack and made a perfectly functional circuit that met all specs :-/. Is there a way to catch this at the schematic check and save time? This sort of thing shouldn't be happening in 2018...
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Forum Post: RE: Preventing a stupid schematic mistake with NMOS back-gates
I should have added that the bad NMOS diode stack (after simulation) just consists of 3 Vgs voltages that don't show any of the back-gate effect on each device's threshold voltage like the good stack does i.e. each Vgs in the bad stack is the same.
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Forum Post: RE: Create a symbol from layout
Thank you for the advices
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Forum Post: RE: Preventing a stupid schematic mistake with NMOS back-gates
A custom schematic check could certainly be added to do this - obviously Cadence can't do this out of the box because it depends on the technology - we have no way of knowing whether the device has an isolated well (or even what type the substrate was) or is just indicating that you want a strong connection to the ground in metal (with substrate ties). I'm sure LVS would normally pick this up, but it's a bit late. I think you could also do it with asserts in spectre to see if the bulk node wasn't zero (obviously these asserts would needed to be included along with the models). A connectivity-based check at check-and-save time would certainly be feasible though. There's several places I've posted example schematic check code - e.g. in this post . It would be easy enough to code a check that looked at the bulk pins of a set of devices and checked that they were connected to a reasonable node in the design. Regards, Andrew.
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Forum Post: Monte Carlo for Verilog A based model file
Hi, I created a symbol using verilogA from 3 file which contains the defination for the other module, I created the following modification in the top level file module FET(Drain,Gate,Source,Sub); parameter real n1= 2; parameter real n2=1; (*cds_inherited_parameter*) parameter real monten1=0; (*cds_inherited_parameter*) parameter real monten2=0; localparam real n1_eff = n1 + monten1; localparam real n2_eff = n2 + monten2; FET_L2 #(.Lch(Lch),.Lgeff(Lgeff),.Lss(Lss),.Ldd(Ldd),.Efi(Efi),.Kgate(Kgate),.Tox(Tox),.Csub(Csub),.Ccsd(Ccsd),.CoupleRatio(CoupleRatio),.Vfbn(Vfbn),.Dout(Dout),.Sout(Sout),.GF(min(Wgate/1.0e-12,1.0)),.Pitch(Pitch),.CNTPos(1),.n1(n1_eff),.n2(n2_eff)) XNCNFET_L2_edge (int_Drain1, int_Gate1, int_Source1, Sub, int_Drain1); and then i created a spectreText of the model and included it in the model library simulator lang=spectre subckt NCNFET_L3_MC1 Drain Gate Source Sub parameters monten1 = 10 monten2 = 10 statistics { mismatch { vary monten1 dist=gauss std=5 vary monten2 dist=gauss std=5 } } ends NCNFET_L3_MC but Im getting the following error:- The HDL cell-view "shobhit" "NCNFET_L3_MC1" "veriloga" does not have view-specific simulation data. To create the data please open and save the view. You may also update the view by executing the following SKILL command: ahdlUpdateViewInfo("shobhit" ?cell "NCNFET_L3_MC1" ?view "veriloga") End netlisting Aug 2 13:26:14 2018 Im using IC6.7 and mmsim15.10
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Forum Post: RE: Is it possible show origin in Allegro
Hi, Yes, I am X PADS user too. The switch you need to turn on is found under (at the top of your screen) -setup/design parameters. Select the Display tab and you will see the Design origin switch. Hit Ok and presto. by the way you can move the origin around just like PADS as well. This was not always the case. until I submitted a write up explaining the benefits of temporarily moving the origin around as a tool to help places graphics quickly. Cheers
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Forum Post: RE: DBID of overlapping components
Hi It depends on what you mean by overlapping components, is it 2 place bounds overlapping, pins overlapping or what define if they are overlapping? You could setup drc checks for this and run through the DRCs. Best regards Ole
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Forum Post: RE: Preventing a stupid schematic mistake with NMOS back-gates
Thanks for the advice and also the link to your code. I'll see what we can be tweaked for this case. I attribute this issue to the pdk not being well thought out, which is kind of poor given that it's a very mature process...
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Forum Post: RE: Monte Carlo for Verilog A based model file
Well, the first mistake is that it makes no sense to put the statistics block inside a subckt. Rather than creating a spectreText view with that in (spectreText views are intended for structural designs really), you should create a text file (say monte.scs) with the contents of that subckt (without the subckt lines) and then include it in your simulation by Setup->Model Libraries in ADE. I have no idea why it would be complaining about shobhit/NCNFET_LC_MC1/veriloga when you've created a module called FET. Even if you created the cell called NCNFET_LC_MC1 but had called the module inside FET (not a good idea), I wouldn't have expected this error. I suspect there's some key bit of information you've omitted to mention - I don't even know why it would be looking at that view. Given the amount of time and effort it took last time to guess what you'd done wrong, I suggest you contact customer support so that somebody can take a look at what you've done rather than going back and forth all the time. I'm not sure I have the patience (sorry...) Andrew.
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Forum Post: RE: Monte Carlo for Verilog A based model file
Thank you Andrew for your time, I'll contact customer service. Regards Shobhit
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Forum Post: RE: how to set a bindkey to display multiple layers ?
Hi Andrew, when I type getVersion(t) in CIW it show "sub-version Ic6.1.5.500.10" . Let me try leSetLayerVisible(list(Mm1" "drawing") t) first and see if it is working thanks Nhumai
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Forum Post: RE: how to set a bindkey to display multiple layers ?
Hi Andrew I have hiSetBindKeys( "Layout" list( list( " 4" leSetLayerVisible(list("nwell" "drawing") t) hiRedraw()) )) ;; hiSetBindKeys it is still doesn't work . It didn't give me any syntax error. It give me the warning like " *WARNING* key 4 non-EF argument must be type string, not symbol *WARNING* key 4 EF argument must be type string, not symbol " Please let me know what happen thanks Nhumai PS. when I type getVersion(t) in CIW it show "sub-version Ic6.1.5.500.10"
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Forum Post: RE: how to set a bindkey to display multiple layers ?
Hi Marben, It is working fine for me. Thanks a lot Nhumai
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