What exact version are you running from Help - About ? If it says 16.6 PXX then that's the base release and it may be an issue. Get the latest hotfix from Cadence Support / Channel Partner. You could also look at reseting the psmpath and padpath.You have set these incorrectly and "occasionally" I have seen issues with this. When you locate the psmpath and click on ... to get the values delete all entries apart from $psmpath, then click on the expand checkbox and then add your library locations. It's unlikely this will help but might be worth a try...
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Forum Post: RE: Capture CIS_Show Footprint
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Forum Post: [AHB eVC]How to send transfers with no IDLE cycles
Hi, I want to send multiple SINGLE bursts with no intervals in between. like 2-2-2-2-2-2-2-2... However, when I use the following source code, I got a couple of IDLE cycles like 2-2-0-2-2-2-0-2-0-2..., and I don't understand why. Can anybody help me? (I am using non_blocking_write api, so there will be no 1 cycle loss between bursts.) struct ahb_trans{ trans_type : vr_ahb_burst_kind; trans_dir : vr_ahb_direction; trans_size : vr_ahb_transfer_size; trans_addr : vr_ahb_address; trans_data : vr_ahb_data; }; extend vr_ahb_master_seq_kind : [ MY_SEQ ]; extend MY_SEQ vr_ahb_master_seq { !ahb_trans; for i from 0 to 10 { gen ahb_trans; non_blocking_write( ahb_trans.trans_addr, {ahb_trans.trans_data}, ahb_trans.trans_type, ahb_trans.trans_size); }; }; * MY_SEQ will be used in MAIN sequence. Appreciate any help.
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Forum Post: RE: [AHB eVC]How to send transfers with no IDLE cycles
I found the problem by setting the log verbosity to full. For some reason, some locked bursts are sent among all the bursts and an IDLE cycle was forced after each locked burst. Although I still don't understand why these unexpected locked bursts are inserted, I solve the problem by explicitly specify the burst.lock == FALSE; Hope this can help someone who encountered the same problem.
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Forum Post: Invalid CDF choice
I have been using some skill code where an instance (pcell) master is replaced with another pcell. The parameters are not the same, so I assumed all the cdf parameters are set to the default value of the new pcell. I do this in combination with clones, doing following steps: Generate all instances from a schematic Select the group I want to clone, and generate synchronous copy clones Descend in on of the clones, and replace the instance master. These steps don't give any problems, in all the clones the master is replaced with my custom pcell. But sometimes, while altering a parameter, I get an error message An invalid CDF choice "netlist" was specified for the CDF parameter "source". My new pcell has a cdf parameter "source", a string. My original pcell doesn't have a cdf parameter "source", so I have no idea where this is coming from. This problem occurs on about 20% of the clonegroups I work on with above procedure. I tried to do something with resetting or clearing cdf parameters, but with no succes. Any ideas??
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Forum Post: Allegro Skill - Convert Shape to Mechanical Symbol
Hi, Anyone please tell me how to convert the shape to a mechanical symbol. Note: It must not be ShapeSymbol. Regards, SkillUser
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Forum Post: How to use a custom netlist procedure (and OSSHNL-116 error)
Hello, I would like to ask some information on how to desing and use a custom netlist procedure. I have this scenario A cell called mycell_1 (of library mylib) has a schematic view. In the schematic, I instance the cell mycell_2 (from the same library) and mycell_2 has a schematic and a symbol view. Then, I add a config view to mycell_1 and select to use the schematic view for both cells. Finally, I try to create a spectre netlist through adexl and all is fine. Next, I add a new view to mycell_2, called "customnetlist" and of type "text". I don't fill in this view, I just want it to exist. Then I call this function in the CIW: (almSetNetlistProcedure "mylib" "mycell_2" 'NetlistTextNetlist ?view "customnetlist") In the config view of mycell_1 I choose to use customnetlist view for mycell_2. Now, when I netlist mycell_1, I get this error: ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'customnetlist veriloga ahdl spectre schematic av_analog_extracted av_extracted netlist', for the instance 'I1' in cell 'mycell_1'. Either add one of these views to the library 'mylib', cell 'mycell_2' or modify the view list to contain an existing view. So, I must have forgotten to specify some other options. Can you help me?
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Forum Post: How to communicate impedance control information to the PCB house from Allegro
All, Our new designs have a lot of differential pairs running around our boards and I want to communicate this clearly to the board house so they can adjust tracks to their process to maintain impedance control. We use the ODB++ functionality to communicate the physical board. I have looked though every file inside the ODB++ file and i see nothing that can be interpreted as netname + impedance value + on this layer information. I have looked through the entire interface of Allegro and see nothing that can do this. So, my question is, how can i extract this information from our finished Allegro design and commuincate it in an effective and useful manner? Robert.
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Forum Post: Existence of Layermap Purpose
Hi everyone, Is there any way to check the ".layermap" file for the existence a specific layer purpose? My goal is to check if given an input layer eg. M0 to check if the purpose "drawing" exists within the ".layermap" file, and if so, to color it with a specific coloring. Is there a specific function that can first search through the ".layermap" and help me perform this check within my procedure? Thank you so much!
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Forum Post: RE: Existence of Layermap Purpose
Hi Everyone, I figured out how to do it, so I'll provide the solution here as a reference for anyone in the future. I used the functions as follows: tfId = techGetTechFile(ddGetObj("lib_techfile")) With the tfId now set I can simply iterate through the techfile's db object for the specific layers i'd like to check. layers = tfId~>layers foreach(layer layers lps = layer~>lps ;This is the layer purpose properties foreach( lp lps if(rexMatchp("specifc purpose" lp) colormarker = "exists"; marks for coloring in another procedure etc ) ) Hope this helped, Thanks!
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Forum Post: how to specify different .dspf file for different instances of the same cell
Hi, I'm wondering if it's possible to specify different .dspf file for different instances of the same cell for post layout sim? I know it's staightforward if there are extracted views, through config-tree thing, but in this case I only have extracted .dspf file. thanks, Kev
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Forum Post: Problem running autorouter from within Allegro
I cannot invoke the autorouter using Allegro PCB Designer Performance16.6 license. Do I have to use the ORCAD PCB Designer Professional license to do this? Thanks, Dan
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Forum Post: RE: Problem running autorouter from within Allegro
By no means. What technique are you trying to get it to run?
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Forum Post: RE: How to communicate impedance control information to the PCB house from Allegro
Nets can have "impedance_rule". A trick used by many fabricators is to set a line width to something easy to pick up on, for example, set a line to 4.876 mils. Then tell them that "all 4.876 mil lines on layer xxx shall have an impedance of 50+/-5 ohms. You can check if "impedance_rule" gets forwarded to ODB++. I personally do not use it. However, with Allegro, why not go ahead and set up the stackup with the correct material values and set the impedance in constraint manager to 50 ohms (or 100 ohm diff) and route away? The Allegro solver is very accurate and uses the same closed-form equations as the fab houses. What differs is actual resin content and thickness of the materials. Speak with the fabricator up-front and get this data and enter it into your material database and let Allegro do its job.
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Forum Post: RE: How to communicate impedance control information to the PCB house from Allegro
When you have custom layer stackup, fabs are not really keen on giving you these infos till you place an order. However usually there is no problem with poolable designs.
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Forum Post: [SV] Constraint solver issue
hello below is a class I use for randomize some settings of a ADC controller RTL. I got the following error stop -create -name Randomize -randomize Created stop Randomize assert ( gpadc_settings0.randomize(lo_thre,hi_thre)); // with c_hilo_thre); | ncsim: *W,SVRNDF (./my_task.v,315|41): The randomize method call failed. Observed simulation time : 22747513300 PS + 0 ncsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints: shortint'(men.VBUSOUT ) + shortint'(men.CHPWR ) + shortint'(men.VBUSIN ) + shortint'(men.VSYS ) >= men_num ; (/proj/pm8282d1/wa/stanzani/pm8282d1_des/r1.0.0/digital/top/dig/sim/test_board/tb/gpadc_pkg.sv,761) ncsim: *W,RNDOCS: These variables contribute to the set of conflicting constraints: state variables: men_num (4) [/proj/pm8282d1/wa/stanzani/pm8282d1_des/r1.0.0/digital/top/dig/sim/test_board/tb/gpadc_pkg.sv, 747] 22747513300 PS + 0 (stop Randomize: Randomize failure) I do not understand where the conflict is. It looks to me than men and *thre are completeely independent variables which are randomized separately but surely there is something I do not understand about the constraint solver operation. typedef struct packed { bit M15; bit M14; bit M13; bit TINT; //12 bit IVBUSOUT; //11 bit VBUSOUT; //10 bit PMODE; // 9 bit GPADC0; // 8 bit CHPWR; // 7 bit VSYS; // 6 bit VBATC2; // 5 bit VBATC1; // 4 bit VBATSNSN; // 3 bit VBATSNSP; // 2 bit VBUSIN; // 1 bit M0; // 0 LSB } t_meas_en_reg; class cl_gpadc_settings; rand t_meas_en_reg men; byte unsigned men_num=4; randc bit[3:0] slow; // slow down the sampling clock frequency rand bit [11:0] meas_off; randc byte unsigned lo_thre[9]; randc byte unsigned hi_thre[9]; rand bit [3:0] stretch; // additional setting time for the acq.phase constraint c_men { men.M0==0; men.M13==0; men.M14==0; men.M15==0; shortint'(men.IVBUSOUT) + shortint'(men.TINT ) + shortint'(men. PMODE ) + shortint'(men.GPADC0 ) + shortint'(men.VBATC2 ) + shortint'(men.VBATC1) + shortint'(men.VBATSNSN) + shortint'(men.VBATSNSP) + shortint'(men.VBUSOUT ) + shortint'(men.CHPWR ) + shortint'(men.VBUSIN ) + shortint'(men.VSYS ) >= men_num ; } constraint c_hilo_thre { foreach(lo_thre[i]) lo_thre[i] inside {[5:64]}; foreach(hi_thre[i]) hi_thre[i] inside {[128:255]}; } // function new (input shortint unsigned min_meas); // min_meas_en_num = min_meas; // endfunction:new function new (); endfunction:new
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Forum Post: RE: Extraction Tech File and LEF-Tech Map file for power grid libray
i think there was a way to capture the lef map created internally, but i don't recall the instructions. if you search COS you might find it. at least that one is easy to create with the lef and ict files. the stream map is not created when you save GDS. it is an input that you need to provide. if you don't have a stream map in your PDK then hopefully you have the design rule manual for the process. there is usually a section that has the mask layers and datatypes.
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Forum Post: RE: cdf Parameter access through OA scripting
Hi Oleg, The simple answer is no. It's in the definition of the CDF, which is stored in the cell metadata property bag (data.dm). It's not stored on the instance. Andrew.
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Forum Post: RE: explicit wire decalration by virtuoso verilog netlister
Off the top of my head, I don't know if this can be done - I can check. However, first I'd like to understand why you'd want this? It's not required in the Verilog language (whereas it is for non-scalar nets). Regards, Andrew.
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Forum Post: RE: skill mode download?
Hi Dan, I'm fairly sure there should be someone at Cadence that can supply the emacs SKILL mode to you but it is most likely out of date in that it will not contain the newer functions or reflect any changes that may have been made to existing function APIs. Is that what you are looking for? I don't use emacs and I don't think that I have a copy of the emacs SKILL mode, sorry. Regards, Lawrence.
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Forum Post: RE: Quickly schematic-viewing a gates file
SimVision has a number of layouts built in that you can specify at the command line, but sadly not a schematic-only one. You can define your own layouts though, so open sSimVision once (no design needed), and open the Schematic Tracer window, close all other windows, and go to the menu Window->Layout->Save and save it as "gates". Now you can do this from teh command line: irun myfile.vg -y mylibs/tsmc18 -access +rwc -createdebugdb -gui -layout gates Explanation: irun is the one-stop front-end which will compile and elaborate your design; -gui opens simvision, and -layout gates tells it to open your saved layout. "-access +rwc" enables schematic connectivity tracing (which would be disabled by default for performance reasons). "-createdebugdb" tells the elaborator to save a special debug database to make SimVision load and trace shcematics quicker.
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