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Hi Andrew, I have the same need. The problem is that I perform a post elaboration of the netlist changing all the input, output, inout ports and declared wires type to a user defined nettype(this is done in a system verilog context). The problem arises since the implicit nets are not declared so their type cannot be changed a simple substitution. Irun assign them the wire default type. So during elaboration a wire type is passed to a user defined nettype(in my case a real net). If the implicit nets are declared their type can be easily corrected to the other ports type. Best regards, Jack

did you try the -port option of attachTerm? see the docs for detachTerm, regarding detaching a port and why it's not allowed.

see if this helps: support.cadence.com/.../L2dBISEvZ0FBIS9nQSEh

if you use report_timing -net, the timing report will separate the cell and net delays into separate lines. you can also turn on the fanout column to see that information. check the documentation for the options.

you need to figure out why that net doesn't seem to have a driver. sounds like something might be wrong with the netlist. as for VDD/VSS, BTS should not be trying to buffer those if you didn't list them in the -nets option.

hard to tell without seeing the design. did you visually check to see if the routing was there in the first case?

Thank you for the prompt response.

i don't think SAF and SAIF are the same, but i'm not familiar with either format.

did you declare your pwr/gnd nets in the .globals file? seems like encounter doesn't know that you have pwr/gnd nets or what they are called.

i'm not sure what you are looking for in terms of what is dumped out. when looking at EM violations, you should look for the "rj" section in the file called "results". Any data points above 1.0 (J/JMax) are violations. If you use the result browser when displaying power/rail results or plots, you can see the list from worst to best, including those below the violation limit.

sounds like this should have worked. were any errors or warnings issued? you may need to file a service request.

you might want to post this to CustomIC and maybe a verilog expert there can help. It seems like the direction is getting mangled from INOUT to OUTPUT somewhere - but I'm not a verilog expert, so unfortunately I can't suggest where to look.

Hi Andrey, You can find the list of variables and their default settings (per tool) by looking in your installation hierarchy, for example for the schematic tool the 'central' .cdsenv is here: `cds_root virtuoso`/tools/dfII/etc/tools/schematic/.cdsenv Maybe you can find an appropriate variable that might help suppress the unwanted warnings? Best regards, Lawrence.

You do not want the black-box function, this i for excluding parts of the design completely and you can't simulate if you do that. You need the MSIE flow; you'll need to snapshots, one with your DUT_1 and the first version of the package, and the second with your DUT_2 and the 2nd version of the package. There is a really good rapid adoption kit (RAK) for MSIE on this page: support.cadence.com/.../cos ;src=wp;q=ProductInformation/Functional_Verification/Incisive_RAKs/Incisive_RAK.htm look under the "Performance" section for the "Incremental Elaboration" RAK.

Historically I've asked people to send me a private message with their email details (actually you have to send a friend request because my profile is such that I only allow private messages from "friends" because I don't want people to bypass the forums and just send me questions directly - I don't have the bandwidth to deal with that). However, since the change in the formatting of the forums and main Cadence site, I can't find out how you'd do that - so I'm trying to find out. Given that I still get occasional random friend requests, it must be possible - I'm just not sure how currently. Once I find out, I'll tell you what to do Dan (or I'll contact you directly via a request). I can send you the existing (old) SKILL mode for Emacs that Lawrence refers to. Regards, Andrew.

The properties are gone, I double checked. As a first solution I'm gonna rename my CDF parameters. It's a bit of a strange error since it only happens in combination with synchronous copy clones, and only on about 20% of the devices. Last question, what is the "instance~>source" variable? Is it to indicate an instance was generated with layout XL. They seem to have it set on "netlist", instances that are manually placed have it on nil. Is there a way to reset it from "netlist" to nil?

Hi, Another question on AHB eVC. For some reason, when the master agent drives the AHB signals (to be specific, HSIZE and HADDR), sometimes there will be a 1ps delay(clock period is 3.75ns). It may or may not happen depend on the seed used. So confused and by checking the log, I dont see any unexpected delay. The logger said that bfm drives the signal at the rising edge of the clock exactly. Have anybody encountered the same problem? Any help or your best guess will be appreciated. Thanks a lot.

The timescale is only needed if your design has a mixture of modules with and without timescales. If you're not interested in simulating and only want to browse the schematic, just invent a timescale: "-timescale 1ns/1ns".

I know, I was only saying that there are too many steps involved in just 'viewing' a gates file Thanks Stephen

Here is a copy : github.com/.../skillmode4.4.tar.gz

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