You know what, I should have checked in a real database, rather than just off the top of my head. I checked in the documentation too. The issue is that "source" is the name of a built-in attribute for instance objects in the database, and so you should never have a CDF parameter called that (it's asking for trouble). Every instance has the attribute (not user defined property) called "source". You can see that by doing instId~>? . Here's what he relevant section of the Virtuoso Design Environment SKILL Reference says (in the chapter on Database Access , in the section at the end of that chapter called Attribute Retrieval and Modification : source: (string) The different sources you can assign to an instance. Valid Values: netlist, timing, dist, test, user The default value is "netlist". I'm not sure anything really uses it any more (it was probably used by older place and route tools, like Block Ensemble, which are long gone). I may be wrong though! I'd never noticed that it existed though, mostly because I'm not aware of anything using it. Regards, Andrew.
↧
Forum Post: RE: Invalid CDF choice
↧
Forum Post: RE: Invalid CDF choice
Thanks Andrew, I already tried do find the chapter explaining the attributes, but with no succes. Everything I know is learned with self study, it's a bit hard to search for something if you don't how it's called :)
↧
↧
Forum Post: RE: Suppressing HDL Parser Warning and port mismatch warnings
Hi Andrew, Your suggestions worked perfectly. Thank you! Lawrence, thanks for pointing me in the right direction. I'll make a note of this should I need to do something similar again. Regards, Andrey
↧
Forum Post: Problem with Sign-off option in EDI
Hello everyone, I'm trying to use the sign-off option available in EDI for optimization and also timing report . Everything goes well till after post route stage, however I somehow trapped in an iterative loop which cannot get out! After setting the RC Extraction mode to be in sign-off level (coupled true) and having the timing analysis mode with OCV ( Delay Calculation Options: engine=aae signOff=true SIAware=true(signoff)). During optimization I encounter: **ERROR: (ENCOPT-7055): use setDelayCalMode -engine [feDC | signalStorm] -SIAware false before running optDesign -postRoute -signoff. and when I want to get a timing report I get the following: "ERROR: (ENCESI-2017): There is no coupling capacitance found in the design. Use setDelayCalMode -siAware false to perform base delay analysis. SI analysis requires the parasitics database to contain coupling capacitance. To perform SI analysis, use 'setExtractRCMode -coupled true' prior to extraction or load a SPEF with coupling capacitance and re-run." the last one is a bit confusing since I already set the -coupled option to be true and it works fine in post route stage (without sign off option). Any idea where is the problem? Regards, Meysam
↧
Forum Post: RE: Problem importing DXF traces
Hi Wild, Thanks for your comments on this, yes I checked it but the problem was that I was deleting everything else on the layout before importing it, I usually do that in Altium to avoid having to assign all the layers again and ask the software to "ignore" the unused layers or the layers that I already have on the design, but apparently this program is a bit different on this matter. Thanks again.
↧
↧
Forum Post: Print Noise Summary after "ANALYSIS DURING TRAN"
Hi, I need to simulate the noise of my circuit at specific points in time after transient analysis. For this I use the "ANALYSIS DURING TRAN", (analysis->tran->options-?output->"ANALYSIS DURING TRAN"). I specifiy a time in actimes, and specify acnames = noise. The analysis runs successfully. However, I am unable to use the "Print Noise Summary" feature. When choosing Print Noise Summary, no dialog pops up, just an empty result window. How can I use the "Print Noise Summary" feature when running noise analysis at specific tran points? Thanks, Mohit
↧
Forum Post: RE: Difference in output of calculator 'pvi' function between ADE XL and ADE L
I was able to identify the problem, I believe I had been using different RF/LO frequencies initially, and these were set a global variables in the ADE XL setup. By disabling them, things seem to be evaluating as expected. Sorry for the red herring! Cooper
↧
Forum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
Hi Mohit, Which IC version are you using? In IC616 and IC617 (at least the latest ISRs which I have on my laptop) I get this: Regards, Andrew
↧
Forum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
Hi Andrew, Thanks for the quick reply. I am also using version 6.1.6-64bit(500.1), so it is strange, but I don't get the similar dialog. Also, if I run an stb or ac at actimes, I can't plot the results from "Results"->"Direct Plot". I have to use the "Results Browser". (Not a problem when I run these analylses the ususal (dc operating point) way). Mohit
↧
↧
Forum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
Hi Mohit, Because I see this question a lot - and there's quite a bit of confusion around the topic of "transient noise summary", I wanted to bring this up. If you have access to http://support.cadence.com please see Article 11793398. Note that you can't get a transient noise contribution summary. The noise contribution summary is only possible in the Spectre small signal noise analyses (AC noise, hbnoise, pnoise). You may have heard that you can run ac noise at every time point during transient analysis and use the transient solution vector instead of the dc operating point bias. However, this is not equivalent to the device contributions in transient noise analysis and there is no way to calculate transient noise device contributions from this data. Because noise is modulated by varying the bias, and the noise correlations between the current time point and all previous time points must be accounted for. This is feasible when the circuit behavior is periodic (pss/pnoise, hb/hbnoise) and in steady state conditions. => Use the noise_on and noise_off options to find out how a particular device or sub circuit affects transient noise output. Now, if you are only interested in printing the noise summary at specific times in a transient analysis, you can use the "actimes" and "acnames" option. (This is essentially what you are doing currently, I believe). It will give you some time-dependent noise contributions, but it is very important to understand that this does NOT give the same results as transient noise. Best regards, Tawna
↧
Forum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
Hi Tawna, Thanks for clarifying a potential confusion in terminology (looks like I don't have access to the support portal). However, I am not running transient noise analysis. I am simply running noise (and stb and ac) analyses at specific timepoints. All I am interested in is small signal behaviour once the circuit is in a steady state. Thus, I use acnames, and actimes feature of the tran analysis. However, the analysis results are not accessible through "Results" menu in ADE. They are only accessible through "Results Browser" (e.g. "Results"->"Direct Plot"->"Equivalent Output Noise" doesn't plot anything, and CIW logs "*Warning* no noise results, can't plot equivalent output noise."). That works for most of my needs. But when trying to sort noise contributions, I need to use the "Results"->"Print"->"Noise Summary". Is it possible to understand why the small signal results are not available with the actimes feature? Thanks, Mohit
↧
Forum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
Hi Mohit, I am able to Results-Print-noise summary when using transient with acnames/actimes. I'm not sure why you aren't able to. You might want to open a Case with Customer Support to look into this. best regards, Tawna
↧
Forum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
I don't think this is something that has been implemented recently - certainly I didn't find anything that suggested that when I did a search. I'm on a plane so can't test some older versions such as ISR1 of IC616 that you're using. It's possible that there may have been a bug then or in the MMSIM version you're using (what is that? It should be shown near the top of the spectre output log file). I'll do some checks on this and the stb analysis once I'm back in the office - but it would be useful to know the MMSIM version to help correlate. Thanks, Andrew
↧
↧
Forum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
Hi Andrew, From the spectre log, the MMSIM version is: 13.11.176 (Linux). Thanks for helping track this down. Mohit
↧
Forum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
Hi Tawna, OK thanks for checking. I will look into contacting customer support. Just FYI, I don't have direct knowledge of our license numbers etc., which is taken care by the computing support. Mohit
↧
Forum Post: RE: OrCAD Capture 16.3 hangs on load
Finally I have moved from OrCAD V16.3 to OrCAD V16.6. I have solved my issue. The OrCAD V16.6 is having amazing update.
↧
Forum Post: ead_workshop - ade-xl error message (1921)
Hi friends from Cadence, My virtuoso is IC6.1.6.500.13. I have an error with ade-xl,when I use the ead_workshop (Rapid Adoption Kit). The ade-xl error message (1921) is the following: "Failed to start new job after %d attempts. Possible reasons could be" "1. The machine selected in the current Job Setup Policy is not reachable." "2. The Cadence hierarchy is not detected, not installed properly or" " not compatible on the machine selected in the current Job Setup Policy." "3. Job Start script %s is not found on the remote machine(s). Simulating others circuits, the ade-xl works without this message of error. Do you know why this error is ocurring in the ead_workshop ? How we could fix this error? Thanks, Rafael
↧
↧
Forum Post: RE: ead_workshop - ade-xl error message (1921)
. . . and, this error appears when I simulate choosing the option "Enable Electrical Data Capture for EAD Flow"
↧
Forum Post: RE: High Fanout nets synthesis encounter
Hi Kari.. I found out the problem. The power nets haven't routed properly and They haven't declared as special nets too. Now It has been figured out. Thanks.
↧
Forum Post: SystemVerilog virtuoso netlister
Hi all, I'm using the SystemVerilog netlister in the virtuoso environment(Launch->Plugins->Simulation->SystemVerilog). My aim is to generate a netlist of the analog circuitry modeled in SystemVerilog. The "digital" glue logic is modeled in a "digital" way while analog blocks are described in "real number modelling". To be more specific I would like to use the cadence EE_pkg or cds_rnm_pkg packages for my custom real types. The problem is that when the netlister traverse the hierarchy and the symbols it declares all the ports as input, output or inout without wandering which types the nets should be. Is there a way to add properties to the symbol such that the netlister is able to identify the correct defined type for the port? How can I indicate to the netlister which type I want the port belong to? Many thanks in advance and best regards, Jack
↧