Hi Jack, In general the netlister is supposed to propagate the types from the code in the view being netlisted. There is a mechanism to allow you to override the propagation by adding a property called "dataType" (of type string) to the pin of the symbol (on the symbol view itself), although I found you also had to add a property called "portKind" too for this to work (e.g. set to "var"). I'm not convinced this really is working correctly, as it only caused it to set the net type on the parent cellView's nets, and not in the I/O of the schematic for which this is a symbol of. Also, this portKind property is not documented; without it I found I got a SKILL error and bits of the netlist were missing. Even this is only available in later IC616 ISRs (ISR10 onwards, I think). My recommendation would be to contact customer support to figure this out properly - this is based on 10 minutes of quick experimentation, and I suspect we need to properly explore this and file CCRs with R&D to get this working correctly. Thanks, Andrew.
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Forum Post: RE: SystemVerilog virtuoso netlister
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Forum Post: vmsUpdateCellViews takes long time to finish
Hi everyone, I'm using the function vmsUpdateCellViews in a SKILL script which aims to update and generate files (netlist.oa, data.dm, etc.) for each cell for a functional view. The script is working correctly. However, I notice that it takes about 40 seconds to update a single cell. Is this how long it usually takes? Or is there something else at play here, like licensing check in and check out times? By my calculations, it would take me about 5 straight days to finish running the script. I'm looking to speed it up as much as I can. I apologize if this is more suited towards contacting customer support. I'm using Cadence Virtuoso IC6.1.7-64b.500.6. Sincerely, Andrey IC6.1.7-64b.500.6. The version of Cadence Virtuoso is IC6.1.7-64b.500.6. - See more at: community.cadence.com/.../36380 The version of Cadence Virtuoso is IC6.1.7-64b.500.6. - See more at: community.cadence.com/.../36380 The version of Cadence Virtuoso is IC6.1.7-64b.500.6. - See more at: community.cadence.com/.../36380
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Forum Post: RE: Update PCB Without Capture Schematic?
You could place the part manually. You'll get an error when you draw the trace.
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Forum Post: RE: hiCreateReportField... passing arguments to its callback
Hello Andrew, Sorry for the late reply. Thank you that is indeed what I need. As usual it was my code. I loaded it into IDE set a few break points and saw what I was doing wrong. Thanks again for taking the time to educate... its really appreciated. -timr
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Forum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
Hi Andrew, Thanks for figuring out the issue. Regarding version upgrade, I will check with the computing support. The OCEAN code is very useful. However, the only output from noiseSummary function is "t". If a filename is given, the function does not create that file. To debug, I broke the function by giving bad parameters, and there were reasonable error messages. I also plotted the noise PSD from the CIW window to make sure that there is data from the simulation. What might be wrong here? Thanks, Mohit PS: I had a suspicion that the problem is in the names of result files. And, I renamed the tran_noise.tran_noise file to noise.noise. But that had not solved the issue. I guess there is a little more indirection while accessing the results..
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Forum Post: IIP3 simulations: qpss/hb vs hb
Hi, What is the difference between obtaining IIP3 of a mixer with qpss+hb engine hb itself? I am getting signficantly different results and I thought at lea "hb" should be consistent. See example PDF attached which compares qpss(shooting_+qpac, qpss(hb)+qpac, hb+hbac. There are many other ways for IIP3 calculations (e.g. rapid IIP3, 3-tone with hb up to running a transient, obtaining HD3 from DFT and converting to IIP3). What is the most reliable / consistent method for switching transistors in a modern 28nm process? (e.g. N-path filters, passive mixers, ...) Thank you!(Please visit the site to view this file)
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Forum Post: RE: Quickly schematic-viewing a gates file
In addition to the approach using a layout, one could write a script that passes the top module of the design to the schematic and fills it. Content of the "schematic_fill.tcl" script is below. You would invoke it like: irun myfile.vg -y mylibs/tsmc18 -simvisargs "-schematic -input schematic_fill.tcl" +gui -s -access +rwc -createdebugdb schematic_fill.tcl: # Get the current design, add it to the schematic, and fill it. array set info [simcontrol info] set scope [lindex [split $info(Design) ":."] 1] # Attempt to select it. select set -type scope $scope # Check if we have something selected. if {[select get -type scope] == ""} { # Nothing selected. Try selecting ":" scope for VHDL. set scope ":" select set -type scope $scope if {[select get -type scope] == ""} { error "Unable to extract top level scope from design." } } # Add the selected scope to the schematic schematic add -selected # Fill the scope schematic invoke Edit>FillModules Please give this a try. Thanks. - Doug myfile.vg -y mylibs/tsmc18
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Forum Post: ADE L Calculation: Numerical (?) issues
I needed to rub my eyes multiple times to believe that. I have these two expressions in my ADE L: dB10(mag(8*c1_dc/c3_dc/6)) + 10 dB10(mag(8/6*c1_dc/c3_dc)) + 10 Clearly they are EQUIVALENT . Just different order. The first produces 24.8607, the second one 23.6113 dB. That's nearly 1dB difference!! c1_dc and c3_dc are nonlinearity coefficients which are extracted from a swept DC analysis. Their values are 100.916m and -4.39371m respectively. According to math, the first one is correct. How can that be?
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Forum Post: RE: ADE L Calculation: Numerical (?) issues
Wow, that's crazy. After more research: www.edaboard.co.uk/cadence-calculator-t328175.html But why does ADE L now silently replace 8.0 by 0 in the expression editor?
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Forum Post: RE: ADE L Calculation: Numerical (?) issues
It's not crazy. I was about to explain that this is because you have integer division. This can be rather useful, but you have to be aware that SKILL works this way (as do many, many other languages). So the 8/6 (left to right) ends up being 1, because both operands are integer. As soon as either operand is a float, the division is a floating point division rather than integer division. So make it 8.0/6 and all will be well with the world. I don't know what you mean about ADE replacing 8.0 with 0 in the expression editor. As far as I know, that does not happen. If it does, you'll have to give more details as to precisely what you're doing that makes this happen. Regards, Andrew.
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Forum Post: RE: IIP3 simulations: qpss/hb vs hb
I would generally expect hb to match qpss (in hb mode). However, there may be some subtle difference in the setup which means they are different, particularly if you are trying to simulate a passive mixer using bsim4 models (or bsim3v3 but I'm sure it's not that at 28nm). This is a well known limitation of the bsim4 model (it's not a simulator issue; it's the model itself). There are several papers on this, which I'm sure have been mentioned before on these forums. Try searching (using the magnifying glass at the top of the page) for "passive mixer" and you'll get some hits that explain the challenges. The solutions are typically either to alter the biassing of the circuit slightly (which isn't always viable), or to change the model to something like psp (also not always under your control). It may be something else, but I can see from your graphs that there's a bit of unusual variation in the curves. Your best bet is to contact customer support ; it's really hard to offer much in the way of concrete help for this without being able to see the problem more closely. Regards, Andrew.
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Forum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
Renaming the output file name won't work - all that will happen is that you make the results inaccessible that way. It has to be consistent with what it's called in the logFile which is the "catalog" for the results. Are you saying that noiseSummary() worked OK and printed to the screen, but not if you specified ?output ? If so, try specifying ?output "./noise.txt" - i.e. put "./" at the beginning to make it write to the current directory. It's possible that you have your SKILL path set (getSkillPath()) so that the working directory is not at the beginning, and so a path without a directory component may get written to another directory. To be honest, spending more time trying to figure this out without seeing any data is a waste of time, when using a version without the bug is much more straightforward. Regards, Andrew.
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Forum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
OK, I will try to get hold of a newer version of MMSIM. Thanks for pointing at the issue. My problem with OCEAN function noiseSummary() is that, it never prints a noise summary (with or without a file name). It just prints a string t, which probably means boolean true. The function plot() does work on the selected noise results. Thanks, Mohit
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Forum Post: Extracting Frequency Component from FFT
Dear all, I wish to extract frequency component from the FFT the result. At the moment, in the ADE XL, in the outputs setup tab, I have such an expression, dft("xxx" 99u 100u 65536 "Rectangular" 1 "default" 1)/dft("yyy" 99u 100u 65536 "Rectangular" 1 "default" 1) After the simulation run, in the results tab, the result of the above expression is a waveform. Then, I have to open the waveform, zooming into 915MHz(as I'm getting many frequency component over a wide band), changing the type from magnitude to real or to imaginary, to get the real and imaginary part of the signal. It's very annoying. I'm wondering if we could do all that with a script, finding the 915MHz component and extract the real and imaginary component. Any help is very much appreciated. Menghan Tool version: ic616 mmsim141
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Forum Post: RE: Update PCB Without Capture Schematic?
It depends on how you want to handle it. With or without DRC? If you just need copper you can place holes in the place where the pins go and force copper to touch. It won't pass any netlist tests and will generate DRCs. But if you want to do it without DRC you need to get the symbol into the netlist. Without a schematic it can be done by File->Export->Netlist w/properties. Take a look at that netlist file and see how it's constructed. If it looks undaunting, edit it and create a matching symbol for the pot. You then do a File->Import->Netlist w/ props. You'll find it'll be asking for a "device file". Hopefully google can help with that. If you decide this is the route to go you can post back up here for a few more details when you get stuck :)
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Forum Post: RE: Allegro PCB Design HDL
Yes you can, but i think you can import them as the jpeg or png format in the Design Entry HDL.
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Forum Post: RE: Extracting Frequency Component from FFT
Hi Menghan, You just need to use real(value(... 915M)) or imag(value(... 915M)) . You could leave this output as is, and add a new output: real(value(calcVal("dftResults") 915M)) etc. This is assuming that the output is called "dftResults". Regards, Andrew.
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Forum Post: RE: Exporting PDF in Allegro PCB Designer
Hello, The PCb Designer Lite cannot export a pdf with the Export-->PDF menu...as it is a lite version
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Forum Post: RE: ead_workshop - ade-xl error message (1921)
I can't think of why it would only fail when enabling EAD. I did a search and couldn't find any other reports of such an issue, so I think you'll need to contact customer support (either directly or via your normal support channel) so that we can take a look. Regards, Andrew.
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Forum Post: RE: how to specify different .dspf file for different instances of the same cell
Kev, I don't believe it's currently possible via the dspf_include mechanism (specifying the DSPF file on the Setup->Simulation Files form). Instead, you'd have to use the "old" flow which is to set up the CDF for the cell to have the termOrder in the spectre simulation information to match the order of the subckt header in the DSPF, and then pick view to use->external SPICE (or something like that) in the hierarchy editor for the instances you want to use each DSPF file. You might need to edit the DSPF files to give different .SUBCKT names though - it's not obvious to me that that would really work (I haven't tried it). This might become possible when DSPF view support is fully ready (it's coming soon), but the best bet for now would be to go to customer support to ensure that your requirements are fully captured. Regards, Andrew.
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