The issue is that when you switch into a view with the normal OSS-type netlisters, they need to have what's called a "shadow" database to contain the information about the I/O (the terminals) of that block plus any hierarchy within (to allow the hierarchy to be traversed). That's not the case here because it's just a text view. This will be coming soon with support for SPICE and spectre text views being added in an upcoming IC617 ISR (I believe), but for now you may need to simply create a stopping view (e.g. called "spectre" which is a copy of the symbol view) and then have your custom netlist procedure know to look alongside for a particular view name and include that text. Something like that. Regards, Andrew.
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Forum Post: RE: How to use a custom netlist procedure (and OSSHNL-116 error)
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Forum Post: RE: functions used inside IDE
Thanks I knew what was the issue and solved it
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Forum Post: binding a layout to schematic and putting pins in the layout
Hello, I have a script which generates a layout transistor pattern. Then i needed to bind this layout to a schematic in order to have it XL happy. I searched in the older links here and i found these functions: lxSetConnRef & bndSetInstsBindingByName. And i searched for them in the manuals to know how they are used, I found that i have to use "lxSetConnRef" first then use the second function. both functions have the condition to have the instances as leaf one, what does it mean?????? I tried that and it worked nicely with the transistor has only one multiplier, but it couldn't work with the other transistors which have more than one multiplier. So can you please tell me: 1) what is meant by leaf instance? 2) How can i make it for transistors consisting of more than one multiplier? About putting the pins in the layout, i thought about it like the following: i just made some brain storming with my self about that. - determine the pins needed to be placed, and their layers (text and box) - Identify every transistor will be connected to which pins. - for a certain transistor, identify their Drains, sources, and gates will be connected to which pins and place them. - check if this transistor if its a dummy so all their terminals will be set to vdd. So please can you tell me what the followed procedures for placing the pins for a pattern using skill script, if you can give a simple sample code it will be nice Thanks Regards, Inas
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Forum Post: RE: How to use a custom netlist procedure (and OSSHNL-116 error)
Thanks for the explanation. Can I "create" this shadow database with SKILL so that the netlister will not complain? It doesn't have to make sense because my netlisting function does two things: 1) it writes an "include" statement pointing to an extracted netlist which defines mycell_2 entirely 2) it instantiates mycell_2 by writing the proper connections, including the supplies the point of this step is that our designers do not want to have the whole definition of mycell_2 inside the netlist of mycell_1 and they do not want to use av_extracted views. Today, for unknown reasons, I get a different error message (well... more than one) stating ERROR (OSSHNL-913): Netlisting failed because terminal 'abc' of instance 'I1' in cellview 'mylib/mycell_1/schematic' does not exist in switch master 'mylib/mycell_2/netlist3' If I set simCheckTermMismatchAction to "ignore" before making the netlist then everything works as expected, but this seems a dangerous thing to do Best regards, Patrik
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Forum Post: RE: Update PCB Without Capture Schematic?
Thanks! Exporting the netlist, editing it, and importing the new netlist worked
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Forum Post: RE: How to use a custom netlist procedure (and OSSHNL-116 error)
Hi Patrik, I think you should be able to do: cv=dbOpenCellViewByType("mylib" "mycell" "mytext" "netlist" "ac") a=dbCreateNet(cv "a") dbCreateTerm(a "a" "input") etc. The idea is that you're creating the database as a non-master database (that's what the "c" is for in the access mode) and the viewType is "netlist". Then you just need to create all the terminals in the database (which you would expect to correspond to the terminals on the symbol). Note that I've not tried doing this with a text view, but I think it should work... probably. Regards, Andrew.
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Forum Post: PSS parametric Analysis in rectifier design
I am working on the design of an energy harvesting (rectifier) block for a passive RFID system working at 5.8GHz,as my PhD thesis. Currently I am working on a Dynamic Threshold Voltage Cancellation technique based on the paper entitled: "High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs", K. Kotani, et al., in IEEE JOURNAL OF SOLID-STATE CIRCUITS. After several months of try, finally I could get a relatively correct response for rectifier PCE, using PSS analysis. As the rectifier circuit is quite nonlinear, in order to get the optimum PCE results I need to sweep the size of the mosfets, and based on another reference ("Power efficient multi-stage CMOS rectifier design for UHF RFID tags, Shu-Yi Wong", Chunhong Chen), there is actually an optimum ratio of transistors' sizes which maximizes the PCE. Considering g= (µn*Wn)/(µp*Wp), while " µn" and " µp" are the electron and hole mobility of the NMOS and PMOS devices. 1. Now I would like to know how I can sweep this ratio as a parameter in PSS analysis. Is there a way which I can define this parameter g as a variable to sweep? 2. When I try to sweep the values of Wp and Wn seperately, it keeps getting the convergence error after a long simulation time. (Itried to change the Options but still no convergence) I would be grateful to have your suggestions in this case. Regards, Sanaz
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Forum Post: RE: PSS parametric Analysis in rectifier design
Hi Sanaz, I would generally advise that you use the parameters capability (variables and parameters assistant) in ADE XL to do this, which would involve setting an expression for Wn and Wp as a function of g (note that I'm assuming that rather than having a variable Wn and Wp you directly set the values of the width of the transistors on the n and p devices). Or you could just have a set of dependent expressions between your variables. However, I'm not sure that this is doable in this case, because there are multiple values of Wn and Wp which give the same g, so how are you going to "sweep" them? You could sweep the values of Wn/Wp as a "paramset" - both ADE L parametric analysis and ADE XL variable sweeps allow you to do this. In ADE L parametric analysis tool you specify that you want to do a paramset sweep and then list the values of the two variables and they will be swept together (rather than orthogonally). In ADE XL you can either list the values of each variable (or use one of the sweep types such as start:step:stop)) and then select both variables in the Data View assistant and Right Mouse->Group as parametric set. In both L and XL you'll need to ensure you have the same number of sweep points for both variables. Not sure that helps, but maybe it will point you in the right direction. Regards, Andrew.
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Forum Post: RE: Design Entry HDL - Packaging matter - Library linking - "chips.prt" not found
305 ERROR Message: Cannot find the chips.prt file in lib.cell:view. Description: The error message is generated when there are either all upper-case or mixed-case values in the cds.lib file used by the design. For example, the following cds.lib file may cause the above problem: DEFINE TEST worklib DEFINE myLIB ../Test/mylib INCLUDE /share/cdssetup/cds.lib Solution: Modify the cds.lib file to contain all lower case values. For instance in the example described above, you can leave the DEFINE, INCLUDE, and values all upper-case, however, change the values for the library names and paths as follows: DEFINE test worklib DEFINE mylib ../test/mylib INCLUDE /share/cdssetup/cds.lib This will solve the problem.
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Forum Post: Custom "Run Mode" in ADE XL
Hello, I'm trying to create a custom run mode where I can test different optimization algorithms (Other than the ones available with ADE XL). Ultimately I would like to add a run mode to the list of available run modes and have the output style of a global/local optimization where the 10 best simulation points are shown. I'm having trouble finding functions/documentation about this so that I can start writing the SKILL code. As a basic example I want to select random design points and display the simulation results. Please let me know if this is even possible. Any help or documents towards this will be greatly appreciated. My ADE XL version is 6.16-64b.500.9. Thank you, Eugene
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Forum Post: changing a pour
I have a pour that was creasted by adding a shape in a route keepin. I've contracted the keepin in shape, but the pour doesn't adjust to stay inside it. I have a few to do, so this would be nicer than redoing them. Tips?
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Forum Post: RE: IIP3 simulations: qpss/hb vs hb
Hi Andrew, Thank you. Yes, I am aware of the BSIM problems and the forum references. My models are utsoi (which are based on PSP). But apart from that, I am seeing these inconsistencies even without switching (e.g. just getting IIP3 of Ron of a MOSFET): IIP3 curve still looks like this: (Please visit the site to view this file) Am I am doing something significantly wrong (in this simple scenario) or can I be very sure that it's indeed the models?
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Forum Post: RE: PSS parametric Analysis in rectifier design
Dear Andrew, Thank you for your response. I guess you are right about the multiple values of Wn and Wp which gives the same g, and at the moment I just need to find the value of g which maximizes the PCE. So the only parameter to sweep is actually the g, and when I could find the optimum ratio, then the sizes of Wn and Wp would be define later based on the load value of the circuit. But I just don't know how do I have to define this Paramset (Wn/Wp) in ADE L and then sweep it! I would be thankful for a more detailed explanation or a reference! Regards, Sanaz
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Forum Post: RE: How to use a custom netlist procedure (and OSSHNL-116 error)
Hello Andrew, thank you, this solved all of my problems Best regards, Patrik
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Forum Post: RE: Custom "Run Mode" in ADE XL
Eugene, Not as far as I know. You should contact customer support as this would probably be an enhancement request (I'm not sure how likely it is that we'd provide a public way to add a run mode though). Regards, Andrew.
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Forum Post: RE: changing a pour
By default the copper shapes should be clipped to the route keepin if you added the shape AFTER then keepin. If this is not the case or you are seeing this there is a user preference you can set Setup - User Preferences - shapes - general and enable shape_rki_autoclip. There is a warning about performance issues. Once set run a Force Update from Shape - Global Dynamic Params - Shape Fill tab and the shapes should be clipped to the keepin.
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Forum Post: RE: changing a pour
Perfect answer. Much appreciated.
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Forum Post: What version of MMSIM has correct actimes/acnames functionality?
Hi, We have these two latest versions of IC and MMSIM installed: IC: IC616.010 & IC616.130 MMSIM: MMSIM_13.11.176 & MMSIM_14.10.765. When using the acnames/actimes functionality to run small signal analyses at transient timepoints, I run into problems with each of these. IC616.010: The OCEAN function noiseSummary() prints no report at all. MMSIM_13.11.176: The ADE does not have access to small signal analyses results. (For example, Results->"Direct Plot" has only the 'tran' results available, OR Results->"Plot Output Noise" is enabled, but plots nothing) MMSIM_14.10.765: Given many time points for actimes (for running small signal analyses at transient time points), spectre runs only the first time point, and ignores all others. IC616.130: The OCEAN function noiseSummary() worked, and have not run into a problem yet. Is there a version of MMSIM that has a correct acnames/actimes functionality? And how easy is it to get those newer versions? (I do not have a lot of control over purchases of software) Thanks, Mohit PS: The details of these problems were discussed in a previous thread: community.cadence.com/.../36394
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Forum Post: RE: PSS parametric Analysis in rectifier design
Hi Sanaz, Could you define Wn=g*Wp in your schematics, enabling you to sweep Wn/Wp=g? Thanks, Mohit
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Forum Post: RE: Custom "Run Mode" in ADE XL
Hi Andrew, Thank you for the reply. I thought this might be the case but wanted to ask just to be sure. Eugene
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