[quote userid="4936" url="~/cadence_technology_forums/f/rf-design/40949/pss-simulation-for-vco/1358505#1358505"]It would be much easier if you uploaded (ideally as an attachment) the entire spectre.out log file rather than just the bits you think are important - there is a lot of info in there which would have captured important parameters, how it had been converging (or not). Just reporting the final error isn't very helpful...[/quote] Hello Andrew,i am still digesting and implemeting your guidance with the manual, i got a perfect harmonic balance as shown bellow. in my personal folder i only have files like ASSURA_TECH.LIB CDS.LIB cdsLibEditor.log and my schematic files that i created using library manager. where can i find SPECTRE.OUT file? Thanks
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Forum Post: RE: PSS simulation for VCO
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Forum Post: OCEAN: How to Check if a Corner is Enabled/Disabled?
Hi, It is well described on the manual how to enable/disable corners. However I could not find a way to check when a corners is indeed enabled or disabled - since all corners are returned from ocnxlGetCorners() function. Thanks for the support.
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Forum Post: RE: PSS simulation for VCO
When you run a spectre simulation, you normally have a log file appear (you've copied and pasted info from it in your first post above). In the banner of that window, it gives the path to the file. If running in ADE L, and when you've not changed the project directory (on Setup->Simulator/Dir/Host), it will be in ~/simulation/ cellName / spectre/schematic/ psf/spectre.out - the three in italics are the test bench cell name, the simulator name, and the view being simulated (so might be a config, might be something else, but commonly is schematic). Anyway, glad you've got it working. Regards, Andrew.
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Forum Post: RE: cds.lib
problem solved. Thanks for your support Stephen.
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Forum Post: RE: Monte Carlo analysis on schematic Vs post layout
THANK YOU very much Andrew for that detailed and very insightful reply. It surely helps
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Forum Post: Stability and transient analysis do not match
Hi all, I'm using virtuoso subversion IC6.1.7-64b.500.21 and spectre subversion 18.1.0.143.isr1. I'm verifying stability in a nested multiloop LDO design, so I've introduced several probes to analyze each of the existing loops individually. The location of poles varies with the load current so two runs are made, one for no load and one for max load condition. One of the loops is showing me -40 degrees PM at high load condition but the transient analysis shows no oscillatory behavior. I know the iprobes from analogLib do not open the loop and should not be affecting the operating point of the circuit, but I'm having a hard time understanding what's the root cause of the different results and how to reconcile them. How to make sure that stb results are reliable? Attached you can see the simulation results. Let me know if anything else is needed (I show only a zoom in the transient response from zero to max current and viceversa)
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Forum Post: RE: Stability and transient analysis do not match
Apologies, I meant to place this thread under custom IC design, not custom IC SKILL
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Forum Post: RE: How to print value of a systemverilog class instance when a breakpoint is hit?
From the trials I made, it appears that the Tcl commands in the -exec string are being executed in the top-level module scope, not the context of where the breakpoint is hit (though I would defer to an expert to confirm/deny that). I was able to hack together a command that does what you want: stop -create -line 308 -file -all - $UVM_HOME/src/base/uvm_heartbeat.svh exec {regexp -line {, scope \((.*)\)} [where] m curscope; value $curscope.obj} However I am wondering if you might be missing out on some of the objection tracing capability in the SimVision GUI. Can you describe the bigger picture of what you're trying to solve with this breakpoint? Maybe we can guide you to an easier solution...
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Forum Post: irun with illegal localparam in list of parameters [12.2(IEEE-2001)].
Hi Cadence, I use irun(64): 15.20-s029 to run some SV files I fetched from the internet. I am getting this error but it seems those are correct syntax in Verilog 2001 and later. How do I fix those? Thank you! file: ../tb/tnoc/rtl/bcm/tbcm_counter.sv localparam int WIDTH = $clog2(MAX_COUNT + 1) | ncvlog: *E,LOCALP (../tb/tnoc/rtl/bcm/tbcm_counter.sv,6|11): illegal localparam in list of parameters [12.2(IEEE-2001)]. module gncorelib.tbcm_counter:sv errors: 1, warnings: 0 module tbcm_counter #( parameter int MAX_COUNT = 3, parameter int MIN_COUNT = 0, parameter int INITIAL_COUNT = MIN_COUNT, parameter bit WRAP_AROUND = 1, localparam int WIDTH = $clog2(MAX_COUNT + 1) )( input logic clk, input logic rst_n, input logic i_clear, input logic i_set, input logic [WIDTH-1:0] i_set_value, input logic i_up, input logic i_down, output logic [WIDTH-1:0] o_count, output logic [WIDTH-1:0] o_count_next ); localparam bit [WIDTH-1:0] INITIAL = INITIAL_COUNT; localparam bit [WIDTH-1:0] MAX = MAX_COUNT; localparam bit [WIDTH-1:0] MIN = MIN_COUNT; logic [WIDTH-1:0] count; logic [WIDTH-1:0] count_next;
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Forum Post: RE: irun with illegal localparam in list of parameters [12.2(IEEE-2001)].
It is legal code, but unfortunately this was not supported in Incisive; you could only have localparam declarations in the module body, not the parameter port list in Incisive. If you can switch to using Xcelium then you won't have any problem with this code; Xcelium supports declaring localparm in the parameter port list. Bear in mind that Incisive stopped being developed (no new features) since 2016!
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Forum Post: RE: irun with illegal localparam in list of parameters [12.2(IEEE-2001)].
Thank you StephenH for the response. I think I am outdated on these tools. Is Xcelium going to replace irun/ncsim?
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Forum Post: RE: irun with illegal localparam in list of parameters [12.2(IEEE-2001)].
Yes, Incisive reached the end of its life in 2016 when Xcelium was born. We do still issue bug fixes for Incisive, but we don't put new features in. Eventually Cadence will stop issuing bug fixes for Incisive, but that's not happening immediately due to some customers who are locked onto Incisive for long-term projects (mainly due to functional safety tool version requirements). Xcelium is based off the Incisive code base, with the addition of the RocketSim multi-core engine and has many new features compared to Incisive. For most users it's a seamless swap, Xcelium even accepts the old irun / nc* commands for backwards compatibility (though it prefers you to use xrun). The only caveat is that you need to get your Incisive licences converted to Xcelium ones, but again that should be a simple process and has the benefit that some things that used to be add-on licences in Incisive become standard in Xcelium, so you get more for your money
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Forum Post: RE: Allegro 17.2 Slot tolerance numbers
There is an option to display this under Manufacture - NC - Drill Legend, check the box for Tolerance drill:-
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Forum Post: cadence allegro 16.6 Software is hanged due to shape modification ?
Hi everyone, i am working on cadence allegro 16.6. in my design i am updating shape,but software is hanged due to shape updates.i could not solve this issue. i could not understand it is happening only in this board file.
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Forum Post: bindkey to display Assembler/ADE XL->options->save
Hi All, Is there anyway to define a bindkey to activate the pop-up window of Assembler/ADE XL->options->save? Thanks for your help! BR
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Forum Post: Mixed signal Static Timing Analysis
Dear all, I am working on a mixed signal design (analog on top) with custom analog and automatic digital implementation. I would like to perform a static timing analysis including analog and digital. I have tried to follow the very good guide provided by https://support.cadence.com/apex/articleattachmentportal?id=a1Od0000007MJxdEAG&pageName=ArticleContent&attachId=069d0000003HOufAAG&sq=null , but I have issues assembling the design in Innovus which look to be related to the fact that the analog blocks have a "fully manual" layout. Does anyone of you have experience in such scenario? If so, would you be so kind to share some documentation, flow, hint, suggestion? On the other hand, I have found the following article on the Cadence blog, https://community.cadence.com/cadence_blogs_8/b/ms/posts/openaccess-oa-based-flow-key-to-enabling-efficient-implementation-of-mixed-signal-design-for-the-smart-devices-era . Does anyone know how to get the presentation/documentation related to it? Thanks a lot in advance for any help/suggestion.
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Forum Post: List of lists: How to add elements to each sub-list?
Hi! Assuming that I have a list of lists: ((1 2) (4 5)) Is there any easy way to add elements in the end of each sub-list? i.e: ((1 2 3 ) (4 5)) or ((1 2) (4 5 6 )) Other example with (("Jamie" "Mike" "Tomas") ("Andrew" Harry")) (("Jamie" "Mike" "Tomas" "Doug" ) ("Andrew" Harry")) Thanks in advance
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Forum Post: RE: List of lists: How to add elements to each sub-list?
Hi, It may depend how you are 'finding' or specifying which sublist to add to. Here's a brief example: nlist = '((1 2) (4 5)) => ((1 2) (4 5)) ; find the list starting with '1' assoc(1 nlist) => (1 2) ; destructively append to that sub-list (i.e. edit it in place) nconc(assoc(1 nlist) '(3)) => (1 2 3) ; inspect the list nlist => ((1 2 3) (4 5)) ; find the list starting with '4' assoc(4 nlist) => (4 5) ;destructively append to that sub-list nconc(assoc(4 nlist) '(6)) => (4 5 6) nlist => ((1 2 3) (4 5 6)) Hopefully this helps? Best regards, Lawrence.
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Forum Post: Importing Mentor Graphics DxDesigner Schematics into OrCAD (v17.2)
Folks, A client of mine exported their MG DxDesigner schematic to me in an EDIF format (actually *.edn), it seems to import when I import from the OrCAD main menu, but there is no schematic generated (*.DSN). When I look at the importation log (edi2cap.log) all I see is a whole bunch of lines saying the same thing, namely: EDIF 200: Info: source line 14: no distance scale defined for current library I get this output 40 times and the log entry exits with the following: EDIF 200 parsing finished Design has no schematics => OrCAD Schematic will not be created Design library has no Symbols => OrCAD library will not be created Comment => Maybe you are converting Netlist project I double checked with the CAD guy doing the exportation and it is a schematic and not a netlist file. Does anybody else get this problem when importing Mentor Graphics schematics? Chris
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Forum Post: RE: OCEAN: How to Check if a Corner is Enabled/Disabled?
I think you'll need to use some axl functions: sdb=axlGetMainSetupDB(ocnxlGetSession()) enabledCorners=setof(corn ocnxlGetCorners() axlGetEnabled(axlGetCorner(sdb corn))) Regards, Andrew
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