The attached "Getting Started with Cadence Verification IP" document describes the steps involved in getting started with a Cadence® Verification IP product. You will find useful information on various aspects of using a Cadence VIP product. community.cadence.com/.../vip_5F00_getting_5F00_started.pdf
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Forum Post: How to get started with Cadence Verification IP (VIP)?
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Forum Post: Covert a circle into a dxf file to a plated hole
I imported a dxf file into PCB designer to serve as the board outline. However; I cannot figure out how to convert the circles into plated holes. What is the easiest method to do this?
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Forum Post: RE: PSS simulation for VCO
Dear yefj, A few suggestions follow... 1. Let spectre compute the frequency since you have specified this is an oscillator. I noticed you are entering the beat freuqency. There is a check box to allow spectre to compute the frequency. 2. With an LC or other higher Q based oscillator, you need to guarantee that sufficient samples are taken over the period of oscillation. You are using an errpreset of "moderate" and I don't see that you have specified a value for maxstep (maximum time step for integration). With an errpreset of "moderate", the maximum integration step size is determined by dividing the time of the simulation (30.48 ns?) by 50. In your example, this is 30.48 ns/50 = 609 ps. However, the period of your oscillator is 74 ps. Hence, the maximum time step is far too large and may result in simulator accuracy errors. I would suggest including a maximum integration time step of, perhaps, 1 or 2 ps (maxstep = 1 ps, for example). 3. Your oscillator waveform is near sinusoidal. Hence, you might consider the use of harmonic balance in lieu of the shooting algorithm. Shawn
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Forum Post: RE: PSS simulation for VCO
Hi yefj, There are examples of how to setup an oscillator - both ring (strongly_nonlinear) and sinusoidal (linear) in the RF_Doc_Database database located in /tools.lnx86/spectre/examples/SpectreRF_workshop/RF_Doc_Database.tar.gz And I believe the instructions are located here: /doc/spectreRFexplorerWorkshop/spectreRFexplorerWorkshop.pdf The best part is...it explains the "why" about how set up the analysis. Great step-by-step tutorials. Also see: Article 2046330 SpectreRF AppNotes and Tutorials - One of Our Best Kept Secrets! on https://support.cadence.com . Best regards, Tawna
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Forum Post: RE: Covert a circle into a dxf file to a plated hole
I don't think you want to do it that way. The recommendation is to make a 1-pin component on the schematic (CIS/Concept level) that gives you the option of connecting that plated hole to your ground net, and as a component, already has the padstack and keepouts set up. As a bonus, you can place and reference this component by Refdes in your EMN/IDF exchange file. We like being able to give the EE's CIS library descriptions like "plated mounting hole for M2 fastner with this size of washer" to place on the schematic. Virtually eliminated those mistakes as the mechanical definition evolves.
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Forum Post: Allegro 17.2 Slot tolerance numbers
Hi All: How do I get slot tolerance numbers from padstack into drill legend. Currently only X tolerance shows up not the Y tolerance Also, slot tolerance does not show up in drill customization chart. Thanks Les
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Forum Post: Set Library source to ddHiCreateCellComboField.
Hi, Could you please show me the way I can set the library source in order to ddHiCreateCellComboField fills with the cell names accordingly? Also I have the same question but for ddHiCreateViewComboField in order to fill according to a given cell name. Thanks and regards, Ivick.
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Forum Post: schematic search/replace criteria combination
Hi guys, I am trying to do such replacement in schematic hierarchy: change all libName_A/cellName_A to libName_B/cellName_A, which means I need to combine libName and cellName together when I do search and/or replace. Anyone know such feature ? BR
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Forum Post: RE: schematic search/replace criteria combination
Yes, on the Find/Replace form, use "master" as the Search For/Replace criteria, and then you specify the lib cell view in each field: (note, you should be careful doing this with PDK components as the CDF callbacks won't be called - I just arbitrarily filled in a lib/cell/view before taking a screenshot) Regards, Andrew
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Forum Post: RE: Set Library source to ddHiCreateCellComboField.
Hi Ivick, The trick is to use ddHiLinkFields. See this little example I just put together: /* abLibCellViewComboExample.il Author A.D.Beckett Group Custom IC (UK), Cadence Design Systems Ltd. Language SKILL Date Jan 12, 2019 Modified By Example of using the enhanced lib/cell/view combo fields that support type-in completion. Simply call abLibCellViewComboExample() to create and display the form. *************************************************** SCCS Info: @(#) abLibCellViewComboExample.il 01/12/19.09:31:51 1.2 */ procedure (abLibCellViewComboExample() let ((grid lib cell view libLabel cellLabel viewLabel browse form) libLabel= hiCreateLabel( ?name 'libLabel ?labelText "Library" ?justification 'right ) cellLabel= hiCreateLabel( ?name 'cellLabel ?labelText "Cell" ?justification 'right ) viewLabel= hiCreateLabel( ?name 'viewLabel ?labelText "View" ?justification 'right ) lib=ddHiCreateLibraryComboField( ?name 'lib ?callback "(ddsUpdateSyncWithForm)" ) cell=ddHiCreateCellComboField( ?name 'cell ?callback "(ddsUpdateSyncWithForm)" ) view=ddHiCreateViewComboField( ?name 'view ?callback "(ddsUpdateSyncWithForm)" ) browse= hiCreateFormButton( ?name 'browse ?buttonText "Browse..." ?callback "(ddsSyncWithForm (hiGetCurrentForm) 'browse 'lib 'cell 'view)" ) grid= hiCreateGridLayout( 'grid ?items list ( list ( libLabel 'row 0 'col 0) list ( cellLabel 'row 1 'col 0) list ( viewLabel 'row 2 'col 0) list ( lib 'row 0 'col 1) list ( cell 'row 1 'col 1) list ( view 'row 2 'col 1) list ( browse 'row 0 'col 2) list ( 'col_stretch 0 0) list ( 'col_stretch 1 1) list ( 'col_stretch 2 0) ) ) form= hiCreateLayoutForm( 'abImportParasiticsForm "Lib Cell View Example" grid ?sizePolicy 'horizontalExpanding ) ;---------------------------------------------------------------- ; Need to both instantiate the form and link the fields so that ; the combo-boxes use the other fields to inform the choices ;---------------------------------------------------------------- hiInstantiateForm(form) ddHiLinkFields( form->lib form->cell form->view ) hiDisplayForm(form) ) ) Regards, Andrew.
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Forum Post: RE: PSS simulation for VCO
[quote userid="383860" url="~/cadence_technology_forums/f/rf-design/40949/pss-simulation-for-vco/1358497#1358497"]1. Let spectre compute the frequency since you have specified this is an oscillator. I noticed you are entering the beat freuqency. There is a check box to allow spectre to compute the frequency.[/quote] Hello Shawn,i was only able to check this option when i switched my PSS to harmonic balance instead of shooting. after checking this option it still gives me an error that i must specify a value,although it disables this option when the box checked. it doesnt allow me to auto calculate the beat frequency. [quote userid="383860" url="~/cadence_technology_forums/f/rf-design/40949/pss-simulation-for-vco/1358497#1358497"]However, the period of your oscillator is 74 ps. Hence, the maximum time step is far too large and may result in simulator accuracy errors. I would suggest including a maximum integration time step of, perhaps, 1 or 2 ps (maxstep = 1 ps, for example).[/quote] There is no maxstep option in the PSS window as shown bellow
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Forum Post: RE: PSS simulation for VCO
Yes i am following the spectrerf manual , i even showed quotes of definitions in my first post to justify the numbers i used. [quote userid="2893" url="~/cadence_technology_forums/f/rf-design/40949/pss-simulation-for-vco/1358498#1358498"]Article 2046330 SpectreRF AppNotes and Tutorials[/quote] I tried to search for that article in the support section.it doesnt show me a result. could you please give me a more specific link of this article? Thanks
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Forum Post: RE: Covert a circle into a dxf file to a plated hole
Depends on what you need to create. If they are circular holes then I suggest to use some padstack-type solution. Be aware that holes with a larger diameter than ~5-6mm are probably getting milled since the PCB manufacture does not have such large drill bits. If for example you need to side-plate a large slot (milling slot) then you should mark this slot on an own-created documentation layer. Then contact your PCB bareboard manufacturer so they understand what needs to be done. Bram
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Forum Post: RE: PSS simulation for VCO
Several points here: Shawn made a small mistake - the auto-calculate for the beat frequency doesn't work with oscillators, since it uses the frequencies on sources in the schematic and you don't have that, so you have to enter a number which is an estimate of the oscillation frequency (or the lowest frequency in the circuit if you have dividers as well) maxstep is on the Options form at the bottom of the PSS (or hb) form. It's a good idea to ensure enough points that the oscillation builds up The presence of diodes or transistors in your circuit isn't enough that you then couldn't use harmonic balance - that doesn't make it "strongly nonlinear". So you might still want to try hb with the harmonics set to "auto". If using hb, use the hb analysis rather than the harmonic balance on PSS - it has better automation (the simulator algorithms are the same, but it's a bit more usable). Make sure you have a long enough transient assist time - you can turn on the option Detect Steady State. Whether you need 1 or 2 in the relative harmonic for the noise analysis depends on the frequency you want to measure the noise at. If your oscillator oscillates at 13GHz, but you have a frequency doubler and you want to use it (and measure the noise) at 26GHz, then you'd enter 2. If you wish to use the oscillation frequency at 13GHz, then enter 1. What it means is that you are measuring the output noise at relHarm*PSSfund+outputFreq where outputFreq is what you're sweeping It would be much easier if you uploaded (ideally as an attachment) the entire spectre.out log file rather than just the bits you think are important - there is a lot of info in there which would have captured important parameters, how it had been converging (or not). Just reporting the final error isn't very helpful... Regards, Andrew.
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Forum Post: RE: Covert a circle into a dxf file to a plated hole
In the end, if you have a padstack, you can set the max min tolerance in the library and count on it showing up in the drill table. B-)
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Forum Post: RE: PSS simulation for VCO
Dear Andrew, Thank you for correcting my error! I appreciate, very much, your insight and correction - as always - I have a lot to learn. Shawn
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Forum Post: RE: schematic search/replace criteria combination
clear, thanks for your help Andrew !
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Forum Post: How to print value of a systemverilog class instance when a breakpoint is hit?
I would like to print "obj" or "obj.m_name" every time the following UVM code line is hit. What should I pass to the -exec switch to make this happen? stop -create -line 308 -file $UVM_HOME/src/base/uvm_heartbeat.svh -all -exec {value obj} The obvious attempt: "value obj", produces an error: ncsim: *E,PNOOBJ: Path element could not be found: obj.
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Forum Post: Monte Carlo analysis on schematic Vs post layout
Hi, Is it more appropriate to run Monte Carlo simulation on circuit schematic or on the post-layout extracted version? Will the mismatches be captured more realistically if the analysis is run on the post-layout extracted version? Thanks.
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Forum Post: RE: Monte Carlo analysis on schematic Vs post layout
There are three reasons why it may be more accurate, but I suspect these are not the effects you are thinking of: The physical dimensions of the devices will be more accurately captured, including the parasitic effects and layout dependent effects (things like stress effects, well proximity effects and so on) Any m-factors on the schematic will be extracted as individual devices. With an m-factored device, the mismatch is applied to the instance rather than the individual devices; it is possible to model the statistical impact of the m-factor but I don't see that commonly done. However, post-layout, each device will (probably) be extracted separately and so mismatch would be applied to each finger separately. You may have parasitics in the netlist as well, which should add to the accuracy of the simulation. I suspect you are wondering whether the effects of good layout matching will be taken into account. Well, the random monte carlo variation is generally capturing the remaining random variation, and not systematic variation due to layout proximity and alignment. If there was some element of that included in the variation of the devices, there might be some benefit in providing some information about the correlation between the devices, but: The models usually don't have this effect included The tools don't extract anything that could be converted into a correlation coefficient Even if they did, it would be hard because the random variables are often rather abstract and are combined using equations in the models to model the overall statistical variation (I sometimes see them called random1, random2 etc - with little resemblance to the physical parameter that may be statistically varying). That said, using capabilities such as mismatch contribution in ADE Explorer/Assembler (a Virtuoso Variation Option feature, or as an ADE GXL feature when using ADE XL) can help identify the variation of which devices contributes most to the variation of the output, and typically these will be the devices for which you need to take greater care on for matching to ensure that all you're getting is the remaining local random variation and not systematic variation due to poor layout. So post-layout statistical simulation will be useful (although it will often be slower of course, especially if you have parasitics). Hope that helps! Regards, Andrew
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