This is covered in the "Getting Started with OrCAD TCL 17.2-2016" manual on the Cadence Support site. The encryption is now done by compiling the script since the orcad:: encrypt command is no longer supported.
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Forum Post: RE: Encryption of Capture tcl script
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Forum Post: RE: vsource parameters cleared when changing source type
Thanks very much Andrew, appreciate the response. Will do.
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Forum Post: Linking OrCAD CIS to MySQL -> Only 1 component per Table Shown?
Here's my setup: Ubuntu server 16.04 running mySQL database (outside network) I imported the example BenchAccess database to get started -- I'll eventually add my own components, but thats irrelevant for now. OrCAD 17.2 running inside a Windows 7 VM on my MacBook Pro inside Virtualbox. I SSH Port Forward the Ubuntu Server MySQL port to my MacBook Pro. I add the connection in windows ODBC connection manager using MySQL ODBC 3.51 Driver. I am connecting to my MacBook in this scenario. I import the connection into OrCAD using the CIS configuration file. All goes ok, connection is made. But then when I try to place a database part, I only see 1 entry for each table... For example, on MySQL here are all some of the capacitors: Where as in Place Database Part, here's what I get: Only the 1 entry. Same holds true for each table. For sanity, I also accessed the table through MySQL Workbench in my VM. All rows are shown. However it should be noted I accessed MySQL through MySQL's own "Connect to Database" tool instead of using Windows' Data Sources. Hoping you guys can provide some insight?
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Forum Post: RE: Linking OrCAD CIS to MySQL -> Only 1 component per Table Shown?
Ok, so as I was posting this I figured out the solution but figured it may be useful to someone in the future. UPDATE YOUR DRIVERS . I reconnected using the MySQL ODBC 8.0 ANSI Driver and all is well.
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Forum Post: RE: Pins denied when converting from circuit to component symbol
By the way, IT have fixed the picture upload. I checked and it appears to be behaving properly now. Regards, Andrew.
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Forum Post: RE: can't plot waveform while simulating in cadence virtuoso via spectre
Hi Andrew, I have checked lots of different websites and also read this thread but I could not solve my issue. Whenever I run a long transient simulation I cannot have the results by getting this error "net /vstore selected but not highlighted". When I run less than 1 ms, I can see the results but when I run more than that which I need 4 ms I cannot see the results. I have also checked my netlist and the nodes that I am looking for are mentioned to be saved there. Any comment or idea? Regards, Mehdi
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Forum Post: RE: can't plot waveform while simulating in cadence virtuoso via spectre
Hi Medhi, The first (pinned) post in each forum is a set of guidelines for posting in the forum. This asks you not to post on the end of old threads (I’ll let you off this time) but more importantly asks you to provide the software versions you’re using. I’d need to know the Virtuoso subversion you’re using (Help->About in any window will tell you) and also the spectre version (this will be in the spectre.out simulation log that appears when you run spectre). Also, if you look in ADE at the Outputs->Save All form at the bottom, does it show the output format you have selected? Regards, Andrew
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Forum Post: RE: How to judge a VIP is a good VIP?
This appears to be a very generic question. However, a good VIP must at the least meet the following criteria: Full compliance with the latest specification. Addresses special use cases. Clearly interprets grey areas in the specification. Support multiple interfaces. Must be easily configurable and quick to integrate with the DUT for faster results. Industry proven stability and reliability. In-built ability to quickly identify issues, say by way of a trace file or a history file. Must be backed by a trustworthy support system and good documentation.
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Forum Post: Design entry HDL schematic symbol to CIS schematics symbol conversion.
What is the best way to achieve this other than manual entry? Thanks, Luis
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Forum Post: RE: Allegro and SharePoint
I would look at Git or SVN first. I use Microsoft GitHub as my remote private repository with Atlassian SourceTree as the local manager. $8 a month...
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Forum Post: RE: Allegro and SharePoint
The only justification I've seen for Sharepoint is other departments need help justifying/sharing it's cost to the business. GitHub is a very effective offsite repo for GIT at $8 a month. Atlassian Sourcetree is our local machine manager.
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Forum Post: RE: spectre +aps simulation: the vsources devices with dc=0 are removed, so the currents through those devices cannot be plot
Hi Marcel https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nWzOEAU It's an Andrew solution, with some more details you should read " If however you have existing voltage sources, you can preserve these by using the preserve_master option. You can add this by going to Simulation->Options->Analog , go to the Miscellaneous tab, and then at the bottom in the Additional arguments field type preserve_master=[vsource] " Kind regards, Marc
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Forum Post: cds.lib
Hi all, Anyone know how to define library in cds.lib? Thanks and regards, Yu
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Forum Post: RE: Pins denied when converting from circuit to component symbol
Thank you very much, both the picture upload works and my simbol convertion works fine.
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Forum Post: RE: cds.lib
Hello Yu. This is documented in great detail under https://support.cadence.com/apex/techpubDocViewerPage?xmlName=settingup.xml&title=Setting%20Up%20Your%20Environment%20--%20Setting%20Up%20Your%20Environment%20-%201.2%C2%A0The%20cds.lib%20File&hash=SettingUpYourEnvironment-1.2cdslibThecds.libFile&c_version=18.09&path=SettingUp/SettingUp18.09/Setting_Up_Your_Environment.html#SettingUpYourEnvironment-1.2cdslibThecds.libFile please do take a look at that. Note that if you are using irun or xrun as your compiler front-end, you can actually avoid cds.lib and hdl.var files completely, these commands take a switch "-makelib" which allows you to define a library and send files to that library. For example: xrun -makelib rtllib src/rtl/*.vhd -endlib tb.sv The above command would compile all the files from the src/rtl directory into a library called rtllib.
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Forum Post: RE: alignment of a pin on a component to a pin on an adjacent component
Hi TiBo, I am sorry that what I am replying is not an answer to your question. I am also looking for SKILL script for aligning two pins. SKILL experts please help.
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Forum Post: RE: Encryption of Capture tcl script
Thanks
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Forum Post: RE: Cadence Skill Syntax Highlighting in Notepad++
Thanks, Very promising. BTW in newer version you need to check force background in Settings > Style Configurator
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Forum Post: RE: *ERROR* (DB-320001): Unable to get the Cadence(R) Design Framework II license feature of "111".
Hi Rena, Nothing obvious jumps out in that case - it could be that somebody has restricted the access to the licenses, or it could potentially be that you're running an old version of the license daemons. I would suggest that you would be best to contact customer support to explore this in more detail. Regards, Andrew.
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Forum Post: PSS simulation for VCO
Hello , i have found that my VCO oscilates 13.45GHZ by converting period to frequency from the transient plot bellow f=1/T, i tried to perform the PSS and PNOISE as following: PSS: tbstat=30.48nsecnsec (the transient of the signal,from the plot bellow the steady state starts after 30.48ns ,tbstat help definition is shown bellow bellow) Beat frequency= 13.45GHZ(its the high common input frequency, from my transient response i calculated the oscilation frequency by f=1/T) PNOISE: Relative frequency: the help shown bellow says we should use 2 because we have diodes in it(so i am not sure, my diodes are used as a varactor) frequency range: i thought to specify the range from zero till the frequency of the oscillation i got fro the transient plot and f=1/T. The final ADEL shown bellow. When i tried to run the PSS first ,it gave me an error shown in the end. Why it gave me an error? my VCO is oscillating fine as you can see in the transient plots bellow. a step by step of what was done shown is bellow. Thanks ***************************************************************************************************** pss: time = 30.08 ns (97.5 %), step = 2.974 ps (9.64 m%) Error found by spectre at time = 30.8517 ns during periodic steady state analysis `pss'. ERROR (SPCRTRF-15050): V(out_p,out_n) is too small to reliably detect the period of the oscillator.Perhaps nodes with insignificant signal levels were chosen, or perhaps the oscillator was never properly started. Analysis `pss' was terminated prematurely due to an error. modelParameter: writing model parameter values to rawfile. Opening the PSF file ../psf/modelParameter.info ... element: writing instance parameter values to rawfile. Opening the PSF file ../psf/element.info ... outputParameter: writing output parameter values to rawfile. Opening the PSF file ../psf/outputParameter.info ... designParamVals: writing netlist parameters to rawfile. Opening the PSFASCII file ../psf/designParamVals.info ... primitives: writing primitives to rawfile. Opening the PSFASCII file ../psf/primitives.info.primitives ... subckts: writing subcircuits to rawfile. Opening the PSFASCII file ../psf/subckts.info.subckts ... Aggregate audit (9:14:04 PM, Fri Jan 11, 2019): Time used: CPU = 1.39 s, elapsed = 1.53 s, util. = 91.1%. Time spent in licensing: elapsed = 31.2 ms. Peak memory used = 58.1 Mbytes. Simulation started at: 9:14:02 PM, Fri Jan 11, 2019, ended at: 9:14:04 PM, Fri Jan 11, 2019, with elapsed time (wall clock): 1.53 s. spectre completes with 1 error, 5 warnings, and 4 notices.
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