First of all, posting this in the Feedback, Suggestions, and Questions forum (which is for questions about the forum system, not for technical questions) is rather minimising your chances of getting a response to a technical question. Luckily I monitor that for mis-posts and moved it to a more appropriate forum. [quote userid="415712" url="~/cadence_technology_forums/f/custom-ic-design/40932/tran-statement-in-spectre"]all print file i am able to view[/quote] What do you mean by "all print file"? Andrew.
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Forum Post: RE: tran statement in spectre
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Forum Post: Plot RMS noise over time with AMS simulator
Hello everyone, I have a delay element made of a current source (pMOS) + capacitor towards GND. I would like to plot the RMS noise on the capacitor over time, after running a AMS simulation I know it is possible to visualize the rms noise over time with a pss+pnoise in specific time instants. But with AMS I can only run Transient Noise or Noise analysis. Also, it seems there is no Multiple Runs option for Transient Noise with AMS. Since the overall circuit is quite complex and non linear, I was thinking to run Transient Noise and to use the calculator, like the example here . However that one is with Multiple Runs, but I don't have that option. Do you know how to do it? Thanks
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Forum Post: RE: tran statement in spectre
print file has all the data points that it to my requirement and application purpose. * *Typ rising waveform curve for model drive_1111 ****** Transient Analysis ( transient1 ) tnom= 25.0 temp= 55.0 ****** x time v(pad) 0.00000e+00 5.45094e-07 4.99965e-13 5.72568e-07 9.54817e-13 6.05099e-07 1.86452e-12 6.72726e-07 3.68393e-12 7.86579e-07 7.32275e-12 9.11369e-07 1.22747e-11 9.88059e-07 1.97167e-11 1.05728e-06 2.96542e-11 1.12824e-06 4.00000e-11 1.19340e-06 6.06916e-11 1.31269e-06 8.00000e-11 1.42186e-06 Manjunath N
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Forum Post: RE: How to define a new standard via
Hi Andrew, Thank you for your help .Your method works Thanks John
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Forum Post: RE: Custom report generation
Try with COMP_PART_NUMBER, it will list all part number assigned with the component. COMPONENT SYM_NAME REFDES REFDES_SORT COMP_PART_NUMBER SYM_X SYM_Y SYM_ROTATE SYM_MIRROR END
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Forum Post: Need Help to Know *W,WKWTLK "Waiting for a Exclusive lock" issue
Hi, I'm using NCSIM v15.20.030 version. Have you seen the below issue while running regression with NCSIM; If so please share your feedback. irun: *W,WKWTLK: Waiting for a Exclusive lock on file '/home/*/run/INCA_libs/irun.lnx86.15.20.nc/.ncrun.lock'. pid:120971 With the above error,the test couldn’t execute and went to block state. Please help in this regard?. Thanks, Regards, Mahee.
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Forum Post: spectre +aps simulation: the vsources devices with dc=0 are removed, so the currents through those devices cannot be plot
Hi there, I have next situation: in some schematics are some vsource(s) used just as nets separators or to probe the currents. In most of the cases type=dc. They are preferred by designers versus iprobe, because vsources symbols are smaller and do not overlap neighbor wires. The problem is that when we use spectre +aps, the currents through vsources without voltage ( or dc=0) are not saved. The iprobes are fine, but as I said the vsources are preferred by some people. I assume that +aps is doing some netlist optimization, removing the dummy devices. I've already read https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/37112/not-to-remove-instances-whose-terminals-are-connected-together . I have some questions: - are the vsources with dc=0 considered as dummy devices? - is there any possibility to preserve all instances of a specific type? From the above thread I've understood that we can preserve all insts, or selected insts. - where I can read about the optimizations done by aps and what are the side effects? I assume that speed is coming with a price. Simulator version: mmsim/15.1.0.isr17 Below is a screenshot of the schematic and the associated netlist. I can probe the currents through bot iprobes and through V3, but not through V1 and V2. If I remove +aps argument from spectre command line, then I can probe the currents through all vsources too. Thank you, Marcel IPRB2 (net020 net021) iprobe IPRB1 (net024 net023) iprobe V3 (net021 net019) vsource dc=100.0m type=dc V2 (net023 net020) vsource dc=0 type=dc V1 (net017 net024) vsource type=dc
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Forum Post: Unable to run an ocean script after receiving the message *WARNING* (infile): not a normal file
Hi, I'm using Virtuoso IC6.1.7-64b.500.21 and the output of spectre -W is sub-version 18.1.0.143.isr1. I'm running some simulations via ocean scripts and sometimes, if there's a bug in the script the simulation will fail (of course). However, after correcting the error and trying to run the script again, I receive a message in the CIW saying: *WARNING* (infile): not a normal file And nothing happens. From that moment on I can't run any ocean script and I keep receiving the same message over and over again. The only "work around" is to close and reopen a virtuoso session.Is there a way to recover from such message without having to restart a session? Regards,
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Forum Post: RE: Need Help to Know *W,WKWTLK "Waiting for a Exclusive lock" issue
Hello Mahee. The answer to this is potentially complex, as it depends on your IT setup as well as the way you run your regression suite. Please login to support.cadence.com and look at the following article which describes the NFS locking and troubleshooting in detail: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nTG5EAM&pageName=ArticleContent
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Forum Post: RE: Need Help to Know *W,WKWTLK "Waiting for a Exclusive lock" issue
Hi Stephen, Thank you for sharing the article. I've to work with IT and do modifying the script accordingly.
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Forum Post: RE: spectre +aps simulation: the vsources devices with dc=0 are removed, so the currents through those devices cannot be plot
Hi Marcel https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nWzOEAU It's an Andrew solution, with some more details you should read " If however you have existing voltage sources, you can preserve these by using the preserve_master option. You can add this by going to Simulation->Options->Analog , go to the Miscellaneous tab, and then at the bottom in the Additional arguments field type preserve_master=[vsource] " Kind regards, Marc
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Forum Post: RE: spectre +aps simulation: the vsources devices with dc=0 are removed, so the currents through those devices cannot be plot
Hi Marc, It is perfect. more than perfect. Best Regards, Marcel
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Forum Post: RE: spectre +aps simulation: the vsources devices with dc=0 are removed, so the currents through those devices cannot be plot
Well, the credit goes to Andrew for writing the solution. ;) Please remember to mention the performance impact to your designers.
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Forum Post: RE: tran statement in spectre
OK, but you didn't say how you are generating this print file. Please read Guidelines for the Custom IC Design Forum as this gives some suggestions as to how to ask a good question - the more precise the question, the more precise the answer or even more likely that you'll even get an answer. I cannot guess... Andrew.
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Forum Post: insert option diasbled
Hello, when i try to insert a photo or anything else in the "insert" options" it just turns the screen into gray . i know that its the wrong formus, didnt know where to address with this issue. Thanks
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Forum Post: RE: Unable to run an ocean script after receiving the message *WARNING* (infile): not a normal file
This is a bit odd. I've found only a single (rather old) report of this happening with a tmpfs filesystem (and we couldn't reproduce it). As far as I can see, SKILL issues this message if the file is not one of three types (from the fstat man page): regular file character device FIFO Can you check what the UNIX "stat" command reports on this file (the one reported in the warning): /usr/bin/stat /path/to/your/file Regards, Andrew.
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Forum Post: Pins denied when converting from circuit to component symbol
Hello ,i have tried to convert the varactor circuit into simbol and integrate it in the main circuit. when i have replace the sources and ground with input pins it gave me 4 warnings when in tried to do check and save (it marked some of the pins by X on them) but when i integrated this simbol into the main circuit the check and save worked. why it put X on my pins? Thanks. sorry usually i accompany my question with a step by step photos , but there is a problem with the cadence website,when i pressed the insert option it just turned the screen gray without poping up the window where i could upload the photo
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Forum Post: RE: Pins denied when converting from circuit to component symbol
Did you try doing Check->Find Marker - it should have given an explanation for the markers? These messages will appear in the CIW too when you do a check and save. My guess is that it might be related to the pin directions but the marker explanation ought to help. I've got IT looking into the image upload (I saw your attempted post into the Logic Design forum which went into moderation - not sure why you asked about image upload in the Logic Design forum). I'll not approve that post because it's not a technical question and it's already being investigated now. Andrew.
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Forum Post: vsource parameters cleared when changing source type
Hello, I am experiencing an issue with the vsource from analogLib. If I change the source type then then all the previously entered parameters in the form are cleared. I am remembering from past experience that the form should remember prior parameters so that you can switch back and forth between source types without having to re-enter them all. It might have something to do with our site setup. Any thoughts on where I could look? Cheers, Phil
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Forum Post: RE: vsource parameters cleared when changing source type
Hi Phil, This is a bug that was introduced in (I think) IC617 ISR10. I have a CCR (with a couple of duplicates) - CCR 1816593. Unfortunately the fix keeps being postponed - it's now not proposed until IC618 ISR5 (probably about June timeframe) and even then it's not committed. Reporting this via customer support and asking for a duplicate CCR to be created may help to bring this forward. Regards, Andrew.
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