A few things to check: Before starting Virtuoso, do you have an INCISIVE or ideally XCELIUM (XCELIUM is the replacement for INCISIVE) release in your path? For example, what do you get if you type "ncroot" or "xmroot" in the terminal window? If you do, which version are you using? "irun -version" will tell you (in the terminal window) In the path returned by step 1 above, can you then do (the bit in italics is the part you'll need to change) and show what it reports? ls -l /export/home/apps/XCELIUM1809_latest /tools/affirma_ams/etc/connect_lib/connectLib/*.pak In your cds.lib do you have something like: SOFTINCLUDE $AMSHOME/tools/inca/files/cds.lib The $AMSHOME is an env var pointing to the path given by step 1 above. It could be a full path - doesn't have to be an env var. It might be that the "configure" step wasn't done for the INCISIVE/XCELIUM release during installation - this builds the connectLib and compiles all the connect modules. The above should give us a clue though. Regards, Andrew.
↧
Forum Post: RE: Error with AMS simulator "Connect rules are not found in your AMS installation"
↧
Forum Post: ideal op amp comparator settings
Hello , i am using ahdlib library component called: OPAMP i want to convert its in a simple comparator for A/D . i want it to see who is bigger and output one of the supply voltages i put: gain: 1.5M freq_unitygain 8M rin: 4M vin_offset:30u ibias:15n slew rate:8M rout: 70 positive supply 1.2 negative supply 0 vref =0. i put two opposite sources switching from 0 to 0.6 at 1nsec period and instead of showing me in the output the replica of source1 it gives me a straight line at 0.8 V where did i go wrong transforming it to comaprator? Thanks
↧
↧
Forum Post: RE: Making a monte carlo simulation component specific
Not currently. There's a change request (CCR 2017541) related to this in the system, but it's not been implemented yet (I think spectre may have the capability - although there are some slight gaps at the moment - but it's not available through the user interface, even in the current IC618 release rather than the rather old version you're using). Regards, Andrew.
↧
Forum Post: RE: ideal op amp comparator settings
I'm not sure why it would have a 0.8V steady output from the description you've given - maybe showing the netlist would help? However, it's certainly not going to work properly - feeding a 1ns period pulse into an opamp with 8MHz unity-gain bandwidth is really not going to work well (or 8MV/s slew rate). Here's how it works with the configuration you've given but a slower frequency pulse. With the period you gave it had a slowly ramping signal as the slew rate and bandwidth of the amp would limit its ability to respond: Regards, Andrew.
↧
Forum Post: RE: ideal op amp comparator settings
Hello Andrew, As shown in your example too,Why does the OPAMP (in the /op node) switches between 0.3V and 0.85V? Its suppose to go from 1.2 till 0. Thanks
↧
↧
Forum Post: RE: PAD on VIA.
Try the attached code. It's not very efficient but should give you an idea about where to start. defun( DE_viaInPinList () let((vias, symSide, layer, pad, padPoly, viaInPinList, outPort) axlSetFindFilter(?enabled '("noall", "invisible", "vias"), ?onButtons '("noall", "vias")) axlAddSelectAll() vias = axlGetSelSet() foreach(sym, axlDBGetDesign() ->symbols foreach(pin, setof(pin, sym ->pins, !pin ->isThrough) symSide = if(sym ->isMirrored, "BOTTOM", "TOP") layer = strcat("ETCH/", symSide) pad = axlDBGetPad(pin, layer, "REGULAR") when(pad ->figure padPoly = car(axlPolyFromDB(pin, ?layer layer, ?padType 'REGULAR)) when(padPoly && exists(via, vias, axlGeoPointInShape(via ->xy, padPoly) && memv(layer, via ->startEnd)) viaInPinList = cons(list(symSide, pin ->xy), viaInPinList) ) ) ) ) if(viaInPinList then outPort = axlDMOpenFile("MISC", "ViaInPadReport.txt", "w") foreach(side, '("TOP", "BOTTOM") fprintf(outPort, "%s:\n", side) foreach(pin, setof(pin, viaInPinList, car(pin) == side) fprintf(outPort, "\t%L\n", cadr(pin)) ) ) axlDMClose(outPort) axlUIViewFileCreate("ViaInPadReport.txt", "Via-in-Pad Report", nil, 20:30) else axlUIConfirm("No via-in-pad found") ) ))
↧
Forum Post: Abstract LEF files with Abstract generator
Hello, everyone, I need you to help me deal with the error of Abstracting LEF files. In the process of "Abstract and Verify step" , I meet these error reminder. ******************************************************************************** Running: defout -lib Abstract_files -cell INVM0R -view abstract.ver -log defout.log -def .abstract/verify/PcsCell.def -ver 5.6 Elapsed Time: 7.8s defout translation completed (errors: 0, warnings: 0). INFO (ABS-15019): Starting Silicon Ensemble *Error* (ABS-15041): Cell INVM0R: Unable to start the target place-and-route system. Check the content of the Target system commandline option, in the Verify step, and ensure that a target system license exists. Also check that the system is on your search path and then try again. *Error* (ABS-15040): Cell INVM0R: Unable to verify abstract view in target place-and-route system. Refer to the place-and-route system's log file in .abstract/verify for more information. INFO (ABS-11901): Cell INVM0R: Step Verify finished INFO (ABS-11900): Cell INVM1R: Step Verify started Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.03s. INFO (DB-120008): oaSocket connection timeout value was set to 2 seconds. ********************************************************************************
↧
Forum Post: How can I use the skill code to save flash symbol or shape symbol?
Hi all; I have completed a skil file to create the flash symbol and shape symbol ,but I could not found a way to save them to disk. Is there a way to save them?
↧
Forum Post: RE: How can I use the skill code to save flash symbol or shape symbol?
axlSaveDesign
↧
↧
Forum Post: RE: How can I use the skill code to save flash symbol or shape symbol?
thanks for your apply, and this function is essentially the Allegro "save" command. What i meant is that there is a skill program (run in design) can create shape symbols and flash symbols ,but I can only use them in current design . More ,What I wanted is that how to save flash symbols and shape symbols to disk.
↧
Forum Post: RE: How can I use the skill code to save flash symbol or shape symbol?
This is relatively difficult to achieve. The best way is to create and run a script using Skill and run a separate session of allegro with the script file. Here's a function example that might help you: defun( AFn_createThermalFlash (name); eg. name = "th395od345id55g45" let((data, cwd, templateFile, fsm, p, scriptFileName, cmd) name = lowerCase(name) data = parseString(name, "th od id g") when(length(data) == 4 data = mapcar('readstring data) cwd = getWorkingDir() templateFile = "[pathToTemplates]/blank_thermal_flash.dra" if(isFile(templateFile) then p = axlDMOpenFile("ALLEGRO_SCRIPT", "flash", "w") if(p then sprintf(fsm "%s/%s.fsm", cwd, name) when(isFile(fsm), axlOSFileMove(fsm, strcat(fsm, ".old"))) scriptFileName = get_filename(p) fprintf(p, "setwindow pcb\n") fprintf(p, "generaledit\n") fprintf(p, "prmed\n") fprintf(p, "setwindow form.prmedit\n") fprintf(p, "FORM prmedit type Flash\n") fprintf(p, "FORM prmedit apply\n") fprintf(p, "FORM prmedit done\n") fprintf(p, "setwindow pcb\n") fprintf(p, "generaledit\n") fprintf(p, "add flash\n") fprintf(p, "setwindow form.thermflash\n") fprintf(p, "FORM thermflash indiam %2.3f\n", cadr(data) / 100.0) fprintf(p, "FORM thermflash outdia %2.3f\n", car(data) / 100.0) fprintf(p, "FORM thermflash spkwdth %2.3f\n", caddr(data) / 100.0) fprintf(p, "FORM thermflash spknum 4\n") fprintf(p, "FORM thermflash spkangl %d\n", cadddr(data)) fprintf(p, "FORM thermflash done\n") fprintf(p, "setwindow pcb\n") fprintf(p, "save_as \"%s\\%s.dra\"\n", cwd, name) fprintf(p, "create symbol\n") fprintf(p, "fillin \"%s\\%s.fsm\"\n", cwd, name) fprintf(p, "exit\n") fprintf(p, "fillin no\n") drain(p) axlDMClose(p) sprintf(cmd, "allegro -s flash.scr -p %s %s", cwd, templateFile) shell(cmd) deleteFile(scriptFileName) axlUIConfirm(lsprintf("Local flash symbol created: %s", fsm)) else axlUIConfirm("Error: Could not create flash script file", 'error) ) else axlUIConfirm(lsprintf("Error: Could not create flash template: %s", templateFile), 'error) ) ) ))
↧
Forum Post: RE: How can I use the skill code to save flash symbol or shape symbol?
thanks a lot I'll try
↧
Forum Post: RE: PAD on VIA.
Thank you so much dave.
↧
↧
Forum Post: RE: ideal op amp comparator settings
Dear yefj, [quote userid="397107" url="~/cadence_technology_forums/f/rf-design/41648/ideal-op-amp-comparator-settings/1360421#1360421"][/quote] As shown in your example too,Why does the OPAMP (in the /op node) switches between 0.3V and 0.85V? Its suppose to go from 1.2 till 0. Di you examine the verilogA code yefj? There is a soft limiting parameter whose default value is 0.50 V. From your description, you did not set the soft limiting value and hence, as shown in the attached verilogA code, it is set to 0.50 V. Note that in Andrew's simulation data, the opamp output voltage swings between 350 mV and 850 mV. These voltage values are about 350 mV above the minimum supply of 0 V and 350 mV below the maximum supply of 1.20 V. Hence, it suggests the limiting voltages are symmetric from the upper and lower suppy voltages and due to the soft limiting default value that you did not change. The verilogA file from the Cadence install directory is attached. Shawn `include "discipline.h" `include "constants.h" // $Date: 1997/08/28 05:45:21 $ // $Revision: 1.1 $ // // // Based on the OVI Verilog-A Language Reference Manual, version 1.0 1996 // // `define PI 3.14159265358979323846264338327950288419716939937511 //-------------------- // opamp // // - operational amplifier // // vin_p,vin_n: differential input voltage [V,A] // vout: output voltage [V,A] // vref: reference voltage [V,A] // vspply_p: positive supply voltage [V,A] // vspply_n: negative supply voltage [V,A] // // INSTANCE parameters // gain = gain [] // freq_unitygain = unity gain frequency [Hz] // rin = input resistance [Ohms] // vin_offset = input offset voltage referred to negative [V] // ibias = input current [A] // iin_max = maximum current [A] // slew_rate = slew rate [A/F] // rout = output resistance [Ohms] // vsoft = soft output limiting value [V] // // MODEL parameters // {none} // module opamp(vout, vref, vin_p, vin_n, vspply_p, vspply_n); input vref, vspply_p, vspply_n; inout vout, vin_p, vin_n; electrical vout, vref, vin_p, vin_n, vspply_p, vspply_n; parameter real gain = 835e3; parameter real freq_unitygain = 1.0e6; parameter real rin = 1e6; parameter real vin_offset = 0.0; parameter real ibias = 0.0; parameter real iin_max = 100e-6; parameter real slew_rate = 0.5e6; parameter real rout = 80; parameter real vsoft = 0.5; real c1; real gm_nom; real r1; real vmax_in; real vin_val; electrical cout; analog begin @ ( initial_step or initial_step("dc") ) begin c1 = iin_max/(slew_rate); gm_nom = 2 * `PI * freq_unitygain * c1; r1 = gain/gm_nom; vmax_in = iin_max/gm_nom; end vin_val = V(vin_p,vin_n) + vin_offset; // // Input stage. // I(vin_p, vin_n) vmax_in) I(vref, cout) (V(vspply_p) - vsoft)) I(cout, vref) <+ gm_nom*(V(vout, vspply_p)+vsoft); else if (V(vout) < (V(vspply_n) + vsoft)) I(cout, vref) <+ gm_nom*(V(vout, vspply_n)-vsoft); end endmodule
↧
Forum Post: RE: ideal op amp comparator settings
Hello Shawn , so in order to overcome this limitation we need to set vsoft=10 instead of vsoft=0.5? parameter real vsoft = 10; Thanks
↧
Forum Post: RE: PAD on VIA.
Hai dave It shows only fully filled vias in the pad but i need to show if it liitle bit touched in the pad that also need to show.
↧
Forum Post: RE: PAD on VIA.
↧
↧
Forum Post: RE: ideal op amp comparator settings
Why would you set it (vsoft) to 10V below the supply rails? That's clearly not going to work (clear if you read the model). In fact, why don't you just use a comparator model (there's one in ahdlLib and also one at https://designers-guide.org/verilog-ams/index.html ) rather than trying to use a general opamp model that you don't understand? Regards, Andrew.
↧
Forum Post: RE: use output signals from other circuits as input for simulation
Thanks. I did almost the same thing sometime ago but I saved the file type as excel file. Which one is better, excel or spectre file?
↧
Forum Post: RE: PAD on VIA.
Hi, try this code. axlCmdRegister( "VOP" `VOP) (defun VOP () axlShell("redisplay") originalVisible = axlVisibleGet() designName = axlCurrentDesign() design_path = axlGetDrawingName() design_unit = car(axlDBGetDesignUnits()) err_count = 0 All_syms = list() ;#### Open temp files to work on #### writeOutFile = outfile("./Via_on_pad_report.log" "w") timeperform = fileTimeModified("Via_on_pad_report.log") fprintf(writeOutFile, "Design name: %s\n", design_path) fprintf(writeOutFile, "%s %s\n\n", "Check Date: ", timeToString(timeperform)) fprintf(writeOutFile, "%s\n", "------------------------------------------------") fprintf(writeOutFile, "%-8s %-8s %-18s\n\n", "Symbol", "Layer", "Drc Location") foreach(sym, axlDBGetDesign()->symbols sym_refdes = sym->refdes Sym_side = if(sym->isMirrored, "BOTTOM", "TOP");end if Sym_pins = sym->pins axlVisibleDesign(nil) ;axlVisibleLayer(strcat("PIN/", Sym_side t)) axlVisibleLayer(strcat("VIA CLASS/", Sym_side) t) ;axlShell("redisplay") axlSetFindFilter(?enabled '(NOALL VIAS) ?onButtons '(NOALL VIAS)) axlClearSelSet() foreach(pin Sym_pins pin_pad = axlDBGetPad(pin, strcat("ETCH/", Sym_side), "REGULAR") pin_pad_bBox = pin_pad->bBox pin_bBox_chk = list(axlMXYAdd(pin->xy car(pin_pad_bBox)) axlMXYAdd(pin->xy lastelem(pin_pad_bBox))) data_in_box = axlGetSelSet(axlSingleSelectBox(pin_bBox_chk)) axlClearSelSet() foreach(item data_in_box err_count = err_count + 1 fprintf(writeOutFile, "%-8s %-8s %-L\n", sym_refdes, Sym_side, pin->xy) );end foreach );end foreach );end foreach ; Close the file and wrap up fprintf(writeOutFile,"Total error found: %d errors\n", err_count) fprintf(writeOutFile, "%s\n", "END OF FILE") close(writeOutFile) axlVisibleSet(originalVisible) axlShell("redisplay") if(err_count > 0 then axlUIViewFileCreate("Via_on_pad_report.log", "Via_on_pad_report" nil ) else axlUIConfirm("No error found.") if(isFile("Via_on_pad_report.log") == t then deleteFile("Universal_via_check.log"));end if ); end if );end defun VOP Luan.
↧