Thanks for your reply. Here i don't want the via outer layer overlap i want inter drill of via overlapped in the pad.
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Forum Post: RE: PAD on VIA.
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Forum Post: RE: PAD on VIA.
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Forum Post: RE: Genus 18.1 cannot resolve compiled, hardmacro, memories
The Genius 18.1 cannot resolve all and we can see that from here only and I also want to say that I have also tried it to get the access of the module but got failed. I was doing the connection between the system and printer but got Epson error code e-01 instead of a positive result.
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Forum Post: RE: Loads of ratsnests after changing component/footprint.
I f number of pins are same then place the updated footprint in the the psm path and use place - > update symbols -> in package symbols select the desired footprints, check ignore fixed property and update pad stack from library. [Note - before updating go to Place->manually and in advanced settings uncheck database and check library]
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Forum Post: RE: Error with AMS simulator "Connect rules are not found in your AMS installation"
Dear Andrew, really appreciate your reply. Below are the checks you suggested: 1) INCISIVE seems to be on my path. "ncroot" gives: /home/micro/eda/Cadence/2016-2017/lnx86/INCISIVE_15.20.010 2) "irun -version" output: TOOL: irun 15.20-s022 3) directory "connectLib" is missing from "/home/micro/eda/Cadence/2016-2017/lnx86/INCISIVE_15.20.010/tools/affirma_ams/etc/connect_lib/". 4) the $AMSHOME env var is not present on my system. The path at step #1 is pointed by the $CDS_INCV env var instead. Please, can you point me on the right track about the configuration step? Thank you for your help. Best regards, Tonio
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Forum Post: RE: 3D Viewer don't works
Don´t use the 3D Viewer, it laggs and is so slow that my computer exploded
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Forum Post: RE: Artwork for bottom layers
When is RMB>Mirror applied? Before import > idf > select file > import? I am using 17.2 version.
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Forum Post: RE: ideal op amp comparator settings
Dear yefj, Please consider using the comparator model as Andrew suggests. I also agree 100% with Andrew that it does not make any sense to set vsoft to 10 if you want the opamp voltage swing to approach 0 and 1.2 V ( the ground and supply potentials). It appears you may not understand what vsoft is and using the opamp model to accomplish your goal is confusing you. Thank you, Andrew, for your suggestion to yefj! Shawn
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Forum Post: RE: Artwork for bottom layers
When importing and the tool prompts you for the 'origin' to place the subdrawing, do the RMB/Mirror; then pick where you want to place it.
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Forum Post: RE: Making a monte carlo simulation component specific
Hi Andrew, thanks for the quick reply, you're amazing!
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Forum Post: RE: Artwork for bottom layers
Are you with OrCAD PCB or Allergro? In my Options: I can only select Active Class and Subclass where the import file will go. I don't see Mirror option.
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Forum Post: RE: Artwork for bottom layers
I'm using Allegro. You should have as a minimum Mirror and Rotate as options when you File/Import/IDF and using the RMB (right mouse button).
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Forum Post: RE: Artwork for bottom layers
Found different method. I don't have to export/import the file in either CAD nor IDF. Under the Manufacture > Drafting > Create Detail > select assembly bottom, component assembly bottom, outline, etc in Color Dialog. Before placing, RMB to select Mirror. Then place them in your choice of Active Class and Subclass. That's it. Anyway, thank you for the help. I appreciated it.
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Forum Post: Using Menu contents for bindkey SKILL to toggle schematic label visibility
I am defining a schematic bindkey to iteratively toggle through visibility of a few label options in the schematic view. Ideally, the bindkey could test label visibility prior to toggling, so one of the iterations is effectively a view all (on) setting. Two of the label types can be toggled through the View menu callbacks - Instance and Terminal labels. I would like to then use the menu text to determine the current label settings. However, the text items of the View menu - schViewMenu~>ToggleTerminalLabels~>hiItemText do not get updated when using the menu callbacks - not until a mouse click on the View menu. This causes the bindkey (SKILL) to have incorrect values. eg : >>_schHiToggleLabels("termLabels") >evalstring(schViewMenu~>ToggleTerminalLabels~>_itemCallback) >schViewMenu~>ToggleTerminalLabels~>hiItemText<< is unchanged. Is there a way to force the View Menu items to update when using SKILL to execute the menu callback items? Why is this?
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Forum Post: RE: VerilogA, one or the other parameter implementation
Hi Andrew, Thank you, blanking out the field with your mentioned display condition in the CDF editor works fine. I'm however not sure how to determine in the code which parameter is filled out (and should be used for the calculation) and which parameter is blanked out (and should not be used for the calculation). I'm initializing them as: parameter real vpk = 0; parameter real dbm = 0; Something like this is wanted (pseudo:) if vpk is filled in z = vpk else if dbm is filled in z = 2*dbm end Testing if a parameter is filled in by testing if it is unequal to 0 is not very neat either. Since the filled in value can also be 0 and the blanked out value also evaluates to 0. Regards, Emiel
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Forum Post: RE: Screw footprint and its keep out region
Thanks for the response. I'll watch the video.
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Forum Post: "Assura has not been installed in this hierarchy" Error
Hello All, When I open Layout XL I receive this message from CIW *WARNING* dlopen: /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115/tools.lnx86/assura/lib/64bit/libavview.so: /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115/tools.lnx86/assura/lib/64bit/libavview.so: undefined symbol: _ZN7QObject13connectNotifyEPKc *WARNING* Failed to open shared object file /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115/tools.lnx86/assura/lib/64bit/libavview.so *WARNING* (LE-104272): Assura has not been installed in this hierarchy. Than I check versions of Assura and IC Design Envirmont $which assura /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115/tools.lnx86/bin/assura $ assura -v Assura (R) Physical Verification Version av4.1:Production:dfII6.1.7-64b:IC6.1.7-64b.500.12 Release 4.1_USR5_HF15 Copyright (c) Cadence Design Systems. All rights reserved. @(#)$CDS: assura_64 version av4.1:Production:dfII6.1.7-64b:IC6.1.7-64b.500.12 05/03/2018 21:53 (sjfhw625) $ sub-version 4.1_USR5_HF15, integ signature 2018-05-03-2129 run on server.adress from /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115/tools.lnx86/assura/bin/64bit/assura on Mon May 6 19:37:15 2019 No mcf file specified ***** Assura terminated abnormally ***** and when check IC design version from help menu, it is IC6.1.8-64b.83 This situation occurs after update cadence tools. Here is also part of my .cshrc file setenv CDS_ASSURA /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115 setenv ASSURAHOME $CDS_ASSURA setenv SUBSTRATESTORMHOME $ASSURAHOME # For Assura-RF setenv LANG C setenv PATH "${PATH}:${CDS_ASSURA}/tools.lnx86/bin" setenv PATH "${PATH}:${CDS_ASSURA}/tools.lnx86/assura/bin" setenv PATH "${PATH}:${CDS_ASSURA}/tools.lnx86/dfII/bin" setenv PATH "${PATH}:${SUBSTRATESTORMHOME}/bin" #setenv ASSURA_AUTO_64BIT ALL alias help_cds_assura '$CDS_ASSURA/tools/bin/cdnshelp &' I am not sure are they relevant but I am also reviecing errors at the begining of IC libGL error: No matching fbConfigs or visuals found libGL error: No matching fbConfigs or visuals found libGL error: failed to load driver: swrast libGL error: failed to load driver: swrast Can any one help me about
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Forum Post: RE: ideal op amp comparator settings
Hello Andrew, Thank you very much for the LINK , i managed to write and simulate the OPAMP i needed as shown bellow. One thing that intrests me is the interaction between "verilog component" and "REAL" netlist component. Regarding Impedance what output impedance my OPAMP will present to the surrounding real components? Thanks
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Forum Post: RE: Loads of ratsnests after changing component/footprint.
You also might try Tools/Derive Connectivity after you've read the new netlist in. Sometimes it will re-connect the lines it can't figure out correctly. Works for me at times. Worth a try.
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Forum Post: RE: PAD on VIA.
You may be better off using Constrain Management tools to do this.
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