Forum Post: RE: VSR not dropping vias to short all pins
It shows the following structure -Ungrouped Terminals - a [(must connect all pins | symbolic_default | signal)] - a_1 a_1 - a_2 a_2 and so forth..
View ArticleForum Post: RE: Fanout missing in OrcadX Presto
Hi Mahimang, I already new about the link you shared with me. But, what i mean is that it is not available into Orcad-X Standard Presto license. Even though it is part of the standard license. I got...
View ArticleForum Post: RE: Is ECAD-MCAD collaboration possible between OrCAD 17.4 and...
Catia V5 is the only MCAD tool we use here. Do Cadence people chime in on questions or is it strictly users here?
View ArticleForum Post: RE: Is ECAD-MCAD collaboration possible between OrCAD 17.4 and...
SPB 17.4 is quite old and as far as I know it will be end of support soon (Just have a look at the Lifetime documents in the Cadence support portal) CATIA V5 does only support IDF 3.0. There is no...
View ArticleForum Post: RE: ViVA - eye diagram entries are not allowing variable names
There's a change request related to this - CCR 2109440. There was some partial support in the past but it didn't work everywhere and so was removed for now. I think you can send the expressions to ADE...
View ArticleForum Post: Including parameters in measurement expression
Hello, I have an established parameter, in this case called "CLOAD" when I use it in the schematic program and I need to call it this it can be done with the curly brackets {CLOAD}. I have a...
View ArticleForum Post: RE: How to access the value of a boolean button within a form...
Hi Andrew, yes example test code below. See condition statement used in proc: UseBoolTest() ; used by app_create_dwin(swin) procedure(DockFormProc() bool1 = hiCreateBooleanButton( ?name 'bool1...
View ArticleForum Post: RE: How to access the value of a boolean button within a form...
Thanks for the sample code. However, this doesn't really explain where you are trying to access the boolean button from (the function UseBoolTest is not called from anywhere), and also the global...
View ArticleForum Post: Switched capacitance / Variable capacitor
I have a question regarding a circuit I saw that is represented as a delay element. I want to understand how this circuit functions as a delay element and is it equivalent to the circuit on the left?....
View ArticleForum Post: How to use axlAddSelectPoly to select shapes, but not to select...
Hello. How to use axlAddSelectPoly to select shapes, but not to select shapes that are empty within the selection range axlAddSelectPoly(poly t) ;t = include voids .
View ArticleForum Post: RE: Finding usage of a cell inside other cells
It will be very helpful to get some insights on this. regards Sid
View ArticleForum Post: RE: How to check a cluster of same net vias spacing, with have no...
any metal to any metal spacing can be used to check for missing cline or shape between the same net vias, as seen in the case of via 5:6 to via 4:6 in the above picture, as these vias are separate....
View ArticleForum Post: RE: How to check a cluster of same net vias spacing, with have no...
So，Is there any other way?
View ArticleForum Post: To open schematic view using bindkey irrespective of config binding
Hi, I want to create a bindkey so that I can descend in a particular schematic irrespective of what view I have set in related config. While using QcRfSchAutoDescend(), it opens the view set by...
View ArticleForum Post: RE: How to check a cluster of same net vias spacing, with have no...
Hoping someone else in the forum can provide an answer.
View ArticleForum Post: ADE Assembler, History name prefix list
Hello, It might be simple one, but I did not find a way to delete the History name prefix list, as shown below. It is a convenient feature in Assembler, but as I keep running new sims, all the old...
View ArticleForum Post: explain/correct my understanding between average/covered in imc...
I'm working on the code coverage. Doing a metrics analysis by default we see overall average grade and overall covered. But when i do a block analysis on an instance i see overall covered grade, code...
View ArticleForum Post: How to generate LIB and LEF file.
Dear Sir, I would like to ask, We got a TSMC 65nm foundry file for IC fabrication but i cant see any LIB and LEF file in the folder. So, please suggest me how to get LIB and LEF file or us how to...
View ArticleForum Post: RE: To open schematic view using bindkey irrespective of config...
Hi Rishab, If you don't open the config view, but open the schematic directly, the descend edit default behavior should rely on viewList instead of config. But maybe you want to use this even when...
View ArticleForum Post: PNR flow
As we don't check for timing during floor plan stage unless it is the engineer concern to check timing, so why do innovus tool won't move forward until timing libraries are read ?
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