Forum Post: RE: SystemVerilog virtuoso netlister
Hi Jack, In general the netlister is supposed to propagate the types from the code in the view being netlisted. There is a mechanism to allow you to override the propagation by adding a property called...
View ArticleForum Post: vmsUpdateCellViews takes long time to finish
Hi everyone, I'm using the function vmsUpdateCellViews in a SKILL script which aims to update and generate files (netlist.oa, data.dm, etc.) for each cell for a functional view. The script is working...
View ArticleForum Post: RE: Update PCB Without Capture Schematic?
You could place the part manually. You'll get an error when you draw the trace.
View ArticleForum Post: RE: hiCreateReportField... passing arguments to its callback
Hello Andrew, Sorry for the late reply. Thank you that is indeed what I need. As usual it was my code. I loaded it into IDE set a few break points and saw what I was doing wrong. Thanks again for...
View ArticleForum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
Hi Andrew, Thanks for figuring out the issue. Regarding version upgrade, I will check with the computing support. The OCEAN code is very useful. However, the only output from noiseSummary function is...
View ArticleForum Post: IIP3 simulations: qpss/hb vs hb
Hi, What is the difference between obtaining IIP3 of a mixer with qpss+hb engine hb itself? I am getting signficantly different results and I thought at lea "hb" should be consistent. See example PDF...
View ArticleForum Post: RE: Quickly schematic-viewing a gates file
In addition to the approach using a layout, one could write a script that passes the top module of the design to the schematic and fills it. Content of the "schematic_fill.tcl" script is below. You...
View ArticleForum Post: ADE L Calculation: Numerical (?) issues
I needed to rub my eyes multiple times to believe that. I have these two expressions in my ADE L: dB10(mag(8*c1_dc/c3_dc/6)) + 10 dB10(mag(8/6*c1_dc/c3_dc)) + 10 Clearly they are EQUIVALENT . Just...
View ArticleForum Post: RE: ADE L Calculation: Numerical (?) issues
Wow, that's crazy. After more research: www.edaboard.co.uk/cadence-calculator-t328175.html But why does ADE L now silently replace 8.0 by 0 in the expression editor?
View ArticleForum Post: RE: ADE L Calculation: Numerical (?) issues
It's not crazy. I was about to explain that this is because you have integer division. This can be rather useful, but you have to be aware that SKILL works this way (as do many, many other languages)....
View ArticleForum Post: RE: IIP3 simulations: qpss/hb vs hb
I would generally expect hb to match qpss (in hb mode). However, there may be some subtle difference in the setup which means they are different, particularly if you are trying to simulate a passive...
View ArticleForum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
Renaming the output file name won't work - all that will happen is that you make the results inaccessible that way. It has to be consistent with what it's called in the logFile which is the "catalog"...
View ArticleForum Post: RE: Print Noise Summary after "ANALYSIS DURING TRAN"
OK, I will try to get hold of a newer version of MMSIM. Thanks for pointing at the issue. My problem with OCEAN function noiseSummary() is that, it never prints a noise summary (with or without a file...
View ArticleForum Post: Extracting Frequency Component from FFT
Dear all, I wish to extract frequency component from the FFT the result. At the moment, in the ADE XL, in the outputs setup tab, I have such an expression, dft("xxx" 99u 100u 65536 "Rectangular" 1...
View ArticleForum Post: RE: Update PCB Without Capture Schematic?
It depends on how you want to handle it. With or without DRC? If you just need copper you can place holes in the place where the pins go and force copper to touch. It won't pass any netlist tests and...
View ArticleForum Post: RE: Allegro PCB Design HDL
Yes you can, but i think you can import them as the jpeg or png format in the Design Entry HDL.
View ArticleForum Post: RE: Extracting Frequency Component from FFT
Hi Menghan, You just need to use real(value(... 915M)) or imag(value(... 915M)) . You could leave this output as is, and add a new output: real(value(calcVal("dftResults") 915M)) etc. This is assuming...
View ArticleForum Post: RE: Exporting PDF in Allegro PCB Designer
Hello, The PCb Designer Lite cannot export a pdf with the Export-->PDF menu...as it is a lite version
View ArticleForum Post: RE: ead_workshop - ade-xl error message (1921)
I can't think of why it would only fail when enabling EAD. I did a search and couldn't find any other reports of such an issue, so I think you'll need to contact customer support (either directly or...
View ArticleForum Post: RE: how to specify different .dspf file for different instances...
Kev, I don't believe it's currently possible via the dspf_include mechanism (specifying the DSPF file on the Setup->Simulation Files form). Instead, you'd have to use the "old" flow which is to set...
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