Cadence Technology Forums

Hi, OrCAD PCB 17.4 has the option File - Export - Downrev, which helps to export the 17.2 version from 17.4. Ask your colleague to down rev design and send you.

The si.env you're describing is to produce a CDL netlist; Verilog-A doesn't make any sense for CDL (which is for physical verification, not simulation). If you want a spectre netlist, you need an ADE license. Regards, Andrew.

Thank you very much for you quick response. So if I want to export netlist for simulation (including VerilogA), which si.env configuration should I use? For example, the "simSimulator" should be "spectre"? And one last question, if I can't have ADE license, how can I export netlist in this case?

I didn't try doing this across corners, but you're going to have to create individual files for each corner anyway. So you'd do: pathToResults="/export/home/username/tools/spectre/adc.raw" listOfSignals=list("o1" "o2" "o3" "o4" "o5" "o6") database="tran-tran" outputDir="./adc.pwl" rdbLoadResults("unbound" pathToResults) rdbWriteToFormat("unbound" outputDir "SPECTRE" list(list(pathToResults list(list(database listOfSignals))))) Unfortunately there's a limitation now that the results browser has to be opened and displayed for the export to happen (otherwise it just returns t but doesn't actually write the data). There's a CCR for this, CCR 1054798. Regards, Andrew

See this article: How to create spectre, hspice netlist using the batch mode OSS translator "si" and which licenses are required? Other OSS based netlisters auCdl, verilog, vhdl, systemVerilog Andrew

Thank you very much for your help. I have tried the tutorial in your recommend article. There must be ADE license to export. PS: The link in My Account panel is incorrect with postfix, please check. Thank you.

It seems that the link is not available anymore. Is there a new workshop about measuring offset and make histogram?

I fixed the link. It used to be to a landing page for all the rapid adoption kits.

Hi Andrew, Thanks for answering. :-) I really hope that, someday, you'll find the time to write the book. From my point of view, having a book on this subject would be a very big plus for all community. Regarding the video, I haven't seen it yet, but I will. Best regards, Pedro

I have a PowerShell script that installs Allegro and from within the script I would like to check if Allegro is already installed. And if it is I would like to see what version and hotfix.

I've no idea what you're asking me to check - I don't understand what's wrong? Andrew

If I click to My Account, I will be redirected to this link https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/43854/%3C%=profilelink%%3E and the 400 Bad Request. You can try yourself.

I'd already tried that (it worked for me) and I tried again, and it still worked. I'll ask IT about it. Andrew.

Cadence_SPB_17.4-2019 + Matlab R2019a 请参考本文档中的步骤进行操作 1，打开BJT_AMP.opj 2，设置Matlab路径 3，打开BJT_AMP_SLPS.slx 4，打开后，设置PSpiceBlock，出现或CEFSimpleUI.exe停止工作 5，添加模块 6，相同 7，打开pspsim.slx 8，相同 9，打开C：\ Cadence \ Cadence_SPB_17.4-2019 \ tools \ bin orCEFSimpleUI.exe和orCEFSimple.exe 10，相同我想问一下如何解决，非常感谢！

Thanks it works. Do you know if there are documentations to analyse DC offset of a simple comparator ?

I assume you'd just do a DC sweep with one input being swept past the static other input. You can turn on the "hysteresis" option on the DC analysis if your comparator has hysteresis and you want to see what happens if you sweep up and then back down again. Andrew.

Hi Team, I am getting the following error while executing a vhd file using XCELIUM1803. Could you please help me to resolve it ? srcs/sample.vhd: xmvhdl_p: *F,DLUNNE: Can't find STANDARD at /tools/cadence/installs/XCELIUM1803/tools/inca/files/STD. xrun: *E,VHLERR: Error during parsing VHDL file (status 2), exiting. Thanks Sarath

Hi Steve, I am having this same problem in xcelium but the two options you mentioned do not work. Is there a more up-to-date option I can use to allow binding of a Verilog module, with input ports only, to a VHDL module with a mixture of input and output ports?

Hi Leo. When you say these don't work, do you mean they cause errors, or are they accepted but don't have the desired effect? Are you able to share an example code or the error you're getting?

Forum Post: RE: How to view a PCB in an earlier version (OrCAD 17.2) which was designed using a later version (OrCAD 17.4) ?

Forum Post: RE: Export Netlist with VerilogA subblock when there is no ADE license

Forum Post: RE: Export Netlist with VerilogA subblock when there is no ADE license

Forum Post: RE: fsdb to pwl

Forum Post: RE: Export Netlist with VerilogA subblock when there is no ADE license

Forum Post: RE: Export Netlist with VerilogA subblock when there is no ADE license

Forum Post: RE: double tail comparator input refered offset voltage measured using cadence

Forum Post: RE: double tail comparator input refered offset voltage measured using cadence

Forum Post: RE: How to set ADE-XL/Maestro to a given position and size

Forum Post: RE: Detect Allegro Version from PowerShell

Forum Post: RE: Export Netlist with VerilogA subblock when there is no ADE license

Forum Post: RE: Export Netlist with VerilogA subblock when there is no ADE license

Forum Post: RE: Export Netlist with VerilogA subblock when there is no ADE license

Forum Post: Matlab cannot open Pspice, to prompt orCEFSimpleUI.exe that it has stopped working！

Forum Post: RE: Export Netlist with VerilogA subblock when there is no ADE license

Forum Post: RE: double tail comparator input refered offset voltage measured using cadence

Forum Post: RE: double tail comparator input refered offset voltage measured using cadence

Forum Post: xmvhdl_p: *F,DLUNNE: Can't find STANDARD at /tools/cadence/installs/XCELIUM1803/tools/inca/files/STD. error while compiling a VHD file

Forum Post: RE: Binding systemverilog modules (module ports' directions)

Forum Post: RE: Binding systemverilog modules (module ports' directions)