Thanks RFinley How do I import gerber files then ? If I choose Import->More->Artwork the dialogue has an option for Gerber 274x... But the filetypes are *.art... The gerber files Im trying to import have extensions such as *.GBL, *.GBP, *.GTL, *.GTP etc If I choose 'All Files (*.*) and try to import one of the gerber files I get the following error... So how do you import (or view) gerber files in OrCAD PCB ?
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Forum Post: RE: Can OrCAD be used to import or view gerber files ?
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Forum Post: RE: Binding systemverilog modules (module ports' directions)
Hi Steve. They don't give the desired effect. The error message remains the same.
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Forum Post: RE: Binding systemverilog modules (module ports' directions)
I think I have a workaround now. The signals appear to exist lower down in the hierarchy where there are Verilog sigs. I will bind to the lower module. xmvhdl_p: *E,CFMPMC (./xcelium.d/run.lnx8664 /.cdssvbind/cds_tmp_svbind00005f9d_1dac2dcf_0x6317a2bc.sva,3|124): Port mode mismatch: Verilog( _rd_n_wr__if.rd_n_o) is mode 'inout'; VHDL(IP_TC18. RD_N_O) is mode 'out'.
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Forum Post: RE: Binding systemverilog modules (module ports' directions)
Hmmm... Are you using a very old simulator version? "cdssvbind" is an artefact of the old binding mechanism from about 5 years ago; it got replaced with a new native bind architecture that works much better. You could try the -nncbind switch with Incisive, or -nxmbind with older Xceliums. This switch became a default a while ago but should be supported as a no-op anyway. Anyway, the old bind architecture may well have problems with cross-language binding, we would need a testcase to know if that's your exact problem though...
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Forum Post: RE: Binding systemverilog modules (module ports' directions)
Yes, I will note the details of the issue down and raise a case later on. I will also take note of these other options. The binding has been moved to a lower level Verilog file which does not exhibit this problem. I can now make progress. When I have completed the SVA task then I will see if I can raise the support ticket and attach a testcase. Thanks for your help.
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Forum Post: How to refer to runs in a mdl loop from outside the loop?
I have a question on something I have running OK but feel there's a better way to run the jobs, as in a loop it. Here is what I have working: alias measurement trans { run tran real arise=cross(sig=V(A),dir='rise,n=1,thresh=pvdda/2, start=0) real afall=cross(sig=V(A),dir='fall,n=2,thresh=pvdda/2, start=0) real outrise=cross(sig=V(OUT),dir='rise,n=1,thresh=pvdda/2, start=0) real outfall=cross(sig=V(OUT),dir='fall,n=2,thresh=pvdda/2, start=0) export real vdd=pvdda export real ppvdd=pvdd export real rdelay=(outrise-arise)*1E12 export real fdelay=(outfall-afall)*1E12 export real delta=(abs(rdelay-fdelay)) export real delay =(rdelay+fdelay)/2 } real f1,f2,fout print fmt("%10s %10s %10s %10s\n","rdelay","fdelay","delta","delay") to="gaout" analysis process_array[]={SS,FF} analysis proces proces=process_array[0] run proces cout=1.2 run trans as r0 print fmt("%10V %10V %10V %10V\n",r0->rdelay,r0->fdelay,r0->delta,r0->delay) addto="gaout" proces=process_array[1] run proces cout=0.8 run trans as r1 print fmt("%10V %10V %10V %10V\n",r1->rdelay,r1->fdelay,r1->delta,r1->delay) addto="gaout" f1=max(r0->delta,r1->delta) f2=max(r0->delay,r1->delay) fout=(f1+f2) print fmt("f1=%g\n",f1) addto="gaout" print fmt("f2=%g\n",f2) addto="gaout" print fmt("fout=%g\n",fout) addto="gaout" I would like to extend it for 10 different process corners, which I can do but thought that there might be a way to do it like this: alias measurement trans { run tran real arise=cross(sig=V(A),dir='rise,n=1,thresh=pvdda/2, start=0) real afall=cross(sig=V(A),dir='fall,n=2,thresh=pvdda/2, start=0) real outrise=cross(sig=V(OUT),dir='rise,n=1,thresh=pvdda/2, start=0) real outfall=cross(sig=V(OUT),dir='fall,n=2,thresh=pvdda/2, start=0) export real vdd=pvdda export real ppvdd=pvdd export real rdelay=(outrise-arise)*1E12 export real fdelay=(outfall-afall)*1E12 export real delta=(abs(rdelay-fdelay)) export real delay =(rdelay+fdelay)/2 } real f1,f2,fout print fmt("%10s %10s %10s %10s\n","rdelay","fdelay","delta","delay") to="gaout" analysis process_array[]={SS,FF} analysis proces int i=0 real couti[]={1.2,0.8} foreach i from{0,1}{ proces=process_array[i] cout=couti[i] run proces run trans as r[i] print fmt("%10V %10V %10V %10V\n",r[i]->rdelay,r[i]->fdelay,r[i]->delta,r[i]->delay) addto="gaout" } f1=max(r[0]->delta,r[1]->delta) f2=max(r[0]->delay,r[1]->delay) fout=(f1+f2) print fmt("f1=%g\n",f1) addto="gaout" print fmt("f2=%g\n",f2) addto="gaout" print fmt("fout=%g\n",fout) addto="gaout" If I change r[i] to r and remove the the f1,f2,fout lines this runs. The thing I haven't figured out is how to refer to the runs inside the foreach loop in the f1, f2, fout lines. Is there a way to do this (I don't need r to be an array, it just seemed like a good way to explain what I was looking for)? I realize that this is not that great an example of what I'm trying to do as in this case the f1,f2 coud be moved into the foreach loop with f1,f2 set to 0: f1=max(f1,r) This works in this case but I'm looking to access each of the runs results outside the loop in the general, is there a way to do that?
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Forum Post: RE: Can OrCAD be used to import or view gerber files ?
If these aren't Allegro-generated gerber files, I wouldn't waste my time trying to import them, sorry. Been there, tried that. You end up with a lot of trial-n-error.
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Forum Post: RE: Dynamic Package Height
This is how we currently handle it too. Maybe I'll submit a ticket for this enhancement.
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Forum Post: How to place pins inside of the edge in Innovus
Hi, I am doing layout for a mixed-signal circuit in Innovus. I want to create a digital donut style of layout (i.e. put analog circuit in the middle, and circle analog part with digital circuits). To do that, I need to place some pins inside the edge to connect to analog circuit (as shown in my attachment), but the problems is that I cannot place pins inside the edge by using "pin editor" within Innovus. Any suggestions to place pins inside? Thank you so much for your time and effort.
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Forum Post: RE: Dynamic Package Height
I believe component height DRCs are intended to measure the height of the component, not involve the thickness of the stackup. I have never heard of layout software that took the board thickness into account. Allegro and Orcad can check for interference between a board assembly and an imported enclosure step file. Can you use this updated method?
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Forum Post: RE: How to get a plot with two ADE XL outputs?
Hi Andrew, Followup question on this. If I have A and B are a set of scalar values pertaining to different corners say (A1,A2,A3) (B1,B2,B3). How do I generate a YvsY plot of (A1 vs B1), (A2 vs B2), (A3, vs B3) in a single step? I'm only able to do this a pair at a time and then drag the individual results into another graph., Over multiple corners it becomes tedious fast.
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Forum Post: RE: Dynamic Package Height
Some component have part (mainly connectors) passing thru the pcb in cutouts. Step file are not always available This kind of compoent have this problem of part passing thru: www.vincotech.com/.../flow-2.html I guess Joewi problem is not just for pins only (i personnaly add a place_bound_bottom with small heigt at pin location)
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Forum Post: RE: Dynamic Package Height
Missing Step models. Quite familiar with that. WFH to study Solidworks with an online service called "Solid Professor". Just have to hide this from our "fake-swamped" MEs.
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Forum Post: RE: How to get a plot with two ADE XL outputs?
Use the waveVsWave function in the calculator. For example: waveVsWave(?x B ?y A) where B and A are the expressions or output for B and A respectively. Andrew.
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Forum Post: RE: How to refer to runs in a mdl loop from outside the loop?
Please contact customer support . I'd love to help but I'm on vacation for a week and this needs some detailed experimentation, most likely. There may be others that can help, but from recall I've not normally seen too much response from the community at large for MDL questions. Andrew.
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Forum Post: Allegro PCB 17.4 Package Symbol Wizard Padstack Browser Preview Failed
Hi, When I use Package Symbol Wizard to make a new package, there is a step to specify the padstack to use for the symbol. I can find all the padstacks but can't see it from the preview window as shown by the picture below. Is there something wrong with my configuration?
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Forum Post: RE: How to refer to runs in a mdl loop from outside the loop?
Enjoy your vacation. We're currently running as is so there's no problem, just looking for more elegant ways to do things as they are more concise and less error prone. I've found you most knowledgeable about MDL (as you say, there are not many people like that) and would be more than happy to wait until you're back from vacation and had some time to catch up with more important matters. Cheers!
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Forum Post: RE: Dark theme on Allegro
I'm pretty sure there is a darktheme on allegro.. I saw it on video tutorials at youtube and at the cadence web page: ( https://www.orcad.com/products/customize-pcb-design-experience) . At the middle of the page there are 5 icons to show 5 diferent GIF images. The last 3 GIFs show "OrCAD PCB Designer Professional" in dark mode.
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Forum Post: RE: Dark theme on Allegro
So... yeah I saw it's available now in 17.4 release. But Allegro does not open by default in dark mode. Where do you set that?
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Forum Post: where and how to get stored skill files in cadence
Hello Can someone help me on how/where can I find the stored skill codes in cadence virtuoso?? Thanks and regards Raegaan
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