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Forum Post: RE: SKILL code to print all the labels in a layout view to a file

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Hi Mallikarjun, It's not my code, but you could use shape~>xy to find the coordinate (origin) of the label. Regards, Andrew.

Forum Post: RE: Suppress: *WARNING* COMBINE attribute library not defined

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Hi Andrew, I found what caused the warnings. However the possibility to suppress them would be useful. Thank you Best regards, Aldo

Forum Post: RE: Shape edit boundary operation invalid

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This could be because your editing results in a Shape Boundary that crosses itself. Try a Database Check as the first instance in case there is "something else" in the database that is related to you Shape editing.

Forum Post: RE: Problem about font

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Thanks Steve. I traied to change the fonts in Options - Design Template, but I don't fix the problem.

Forum Post: RE: expression problem from ac sweep

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Dear yejf, > but in our VCO as shown bellow there is no ac current source,so how it's equivalent regarding > the impedance that it will present in the actual system? The impedance you are supposed to simulate is the impedance that the inductor will see. The impedance you are computing is from node v_vco to ground. If that is the impedance the inductor will see in your VCO, that is the correct impedance to simulate. > in our varactor there is no "two sides" as in the capactior shown in the schematics bellow. I do not understand how the varactor will vary its capacitance in your VCO circuit as there is no DC isolation of its bottom terminal from its top terminal. You can only change its capacitance with a change in DC voltage across the varactor. You need to include an AC coupling capacitor if you do not have a means to isolate the DC voltage of your varactor bottom terminal. I think you need to study other VCO designs in the literature as it appears your design and the capacitance voltage characteristic you plot need some design effort. Is this a school project or an actual design? This forum is focused on solving Cadence related issues. Shawn

Forum Post: RE: Deleting PSF data in Simulation

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Yes, I am using ADE L. So ADE XL automatically creates a new directory for the data in simulation, while ADE L overwrites every time ?

Forum Post: Cadence Virtuoso/Design Framework Compatibility with MATLAB

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Hello, I would like to use Cadence Design Framework/Virtuoso/Spectre to simulate with MATLAB using cds_srr and the Spectre Matlab Interface. FIrst: 1) How do I install this interfacing function - is their instructions for this ? Second: 2) How do I know they will be compatible. I am using Cadence Virtuoso IC6.1.7 base version for now, with MATLAB 2018 in Linux/Unix. Thank you.

Forum Post: Orcad Tcl_Create Library Part from Excel File using TCL

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Hi Team, Greetings!! I am working to write a tcl code to create the library parts and add the user properties from Excel file(eg., Resistor_olb.xls) Against this Excel File I need to read the cells and create parts then add User properties for that part. Please advise how to achieve this. Also I request you to provide some sample tcl programs regarding this task. Thanks in Advance. Regards, dvk

Forum Post: How to define a new standard via

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I’m trying defining a new via with SKILL.I’ve try using function techCreateStdViaDef to do this but it seems not work.My technology file doesn’t have the new via’s definition and I can not create the via to my cell.Are there any other things I should do or any other functions I should use?By the Way,I’ve also tried defining a new via by modifying my technology file manually and I succeeded,but I still want to succeed with SKILL? Regards John

Forum Post: RE: How to define a new standard via

Forum Post: RE: How to define a new standard via

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Hi John, I think we need a little more info about how exactly you make the call to techCreateStdViaDef (..), it's return value and whether you get any errors. There's a lot of things that can go wrong like not having a valid techfile id, specifying invalid layers etc... Max

Forum Post: Update symbol with added pad

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Hello, I'm working with Orcad Professional 17.2. I've a pcb 100% routed. I've to add a hole into a symbol. I edited symbol in library and generated .psm file. If I try to update (with "Update symbol padstack from library") and a error occurs: 'SKIIP' symbol starting to refresh: ERROR(SPMHNI-271): 1 pins found in library symbol, but missing from the symbol in the physical design. They are: 33 Anyone can help me? Thanks Stefano

Forum Post: RE: Macro Placement in INNOVUS

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Thanks.. but now I'm facing another problem.. I want to place physical design of memory macros in another main design.. How to do that??

Forum Post: RE: Macro Placement in INNOVUS

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Thanks.. but now I'm facing another problem.. I want to place physical design of memory macros in another main design.. How to do that??

Forum Post: Placing of physical design into another physical design in innovus

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I want to place physical design of memory macros that I have created separately in another main design in innovus.. How to do that??

Forum Post: RE: Update symbol with added pad

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By the look of it, you haven't added a hole, you have added a Connect Pin. Since the Connect Pins are controlled from the Schematic, you will need to update the Part in the Schematic to Add this Pin and then load an updated netlist to use this footprint. (You will certainly need to do this if you want the added Pin to be connected) IF you don't need the additional Pin to be connected, you can delete the Pin Number Text from the added Pin to change it to a Mechanical Pin (not part of the netlist) and then you will be able to save the changed Package Symbol and update it in the board.

Forum Post: RE: transient output file option in pspise

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No, you get the ".PRINT" to the output file, or the Simulation results from the Probe window. Rather than scratching around with text files, the PSpice Systems Option offers comprehensive integration with MATLAB if that is your aim.

Forum Post: RE: Update symbol with added pad

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Solved. Sorry but I'm newbie :-) Thank you very much Stefano

Forum Post: RE: Deleting PSF data in Simulation

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Yes, although ADE XL (Options->Save) does allow you to control how many history points are kept, or whether you want it to just keep overwriting. ADE L does have some capability to write into new results directory each time (e.g. when using distributed processing), but in general it overwrites the results each time. Andrew

Forum Post: RE: add_ignore_pins create_ccopt_clock_tree_spec

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Hi Chetan, I have read these articles, good ones. But this does not answer this question. I have the same message and I want to understand why CCopt is modifying the native spec file to add ignore pins to a skew group. Regards, Hatem
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