Forum Post: RE: Troubleshooting Signal Integrity Issues in Custom PCB Design...
Hi Emmanuel, 1.General design best practices for reflection are avoid impedance mismatching and big discontinuities like a via stub. 2. Cadence Sigrity Reflection workflow allow you to quickly identify...
View ArticleForum Post: Deep Nwell in gpdk180nm
Hello, I think there is no template available by default for Deep Nwell creation in layout for generation gpdk180nm. I want to know how can we manual do that in this technology such that it work fine...
View ArticleForum Post: RE: Using text files to define spectre analysis with monteCarlo
Please contact customer support about this (submit a support case after logging in). Please ask the application engineer who picks up the case to contact me - we can then see whether a potential (not...
View ArticleForum Post: RE: About Allegro max stacked via count in DFF rule
Hi zpofrp, so you are stating that the uvia is not counted, only the bbvias - is that correct? You mention that " Via_L5_L6" is a PTH so I am little confused by this... Can you tell us if the uvias are...
View ArticleForum Post: RE: Get level of hierarchy of part
Thanks, this gives the hierarchy level of selected part.
View ArticleForum Post: RE: DFA circle will not appear while placing components in...
I don't get to use this very often, and I'm idle at the moment. I found out the legacy DFA table is rolled into constraints manager. But, the old tricks to get DFA assembly to work are dormant. If you...
View ArticleForum Post: RE: Model ADA4351 - Errors in Model
What I take away from your reply is that Cadence is adding features from LTspice into PSpice. Are there any other ones you know about?
View ArticleForum Post: RE: About Allegro max stacked via count in DFF rule
There are laser via and mechanical via in the package deign. The PTH is Plating Through Hole, usually it through the Core layer. I don't defined the uvias in the bb via definitions. I have never used...
View ArticleForum Post: RE: About Allegro max stacked via count in DFF rule
II know the UVIA is microvia. so i can set the PTH is BBVIA, the laser via is MicroVia. But i dont think it is going to solve my problem. i want to show DRC for more than a number than through the...
View ArticleForum Post: coloring pins
hello is there an easy way to color the pins based on the xy coordinates? i have a list of the xy coordinates for about 100 pins. i do know that i can color them one by one but i would like to find...
View ArticleForum Post: RE: update layout creates a Rectangle "Board Geometry/Top_Room"...
Hi John, thanks for the reply. I did try this approach but the software doesn't seem to recognize it as a room. I saw the rectangle was assigned a "FIXED" property automatically which I cannot figure...
View ArticleForum Post: Fatal error during callibre view
Dear Cadence team, i am using cadence virtuoso (IC6.1.7-64b.500.19), i have design a schematic in spectre and its layout. When symbol of schematic is used in new cell and copy its layout and rum pex,...
View ArticleForum Post: RE: Create Menu/Window with TCL to fill a user defined Title...
OK,that's so kind of you,I've always wanted an GUI similar to Orcad Capture's built-in "Find And Replace Text Utility" interface, such as having a user input box "find what", a file output path and...
View ArticleForum Post: RE: Fatal error during callibre view
Since Calibre (and the interface to it which generates the calibre view) is not a Cadence tool, you would be better off raising this with Siemens EDA’s customer support (since it is their tool). I...
View ArticleForum Post: Issue while using dbLayerAndNot()
Hello, I am working on a script to place routing blockage layers over an IP using the prBoundary. To derive the XOR data between the respective pins and the PR boundary, I’m using the dbLayerAndNot()...
View ArticleForum Post: Import a reference design into OrCAD
I got a reference design that is supposed to be made in OrCAD, but i cannot open the PCB file. The files in my Zip looks like this, can anybody confirm that this looks like an OrCAD project?
View ArticleForum Post: RE: Import a reference design into OrCAD
The schematic definitely looks to be from Cadence. The board file looks like it might be Mentor Graphics Pads file as they use .pcb extension. Maybe there are others(?)
View ArticleForum Post: stb Results Documentation
After running stb analysis, I right-click in the maestro Results tab -> Direct Plot -> Main Form, and from there I can make the tool add the desired expressions to my test's Output Setup, for...
View ArticleForum Post: RE: Import a reference design into OrCAD
I use Altium at work, and Altium has .pcb extensions but it wont open there. I downloaded a 30day trial of OrCAD to try to open the files, but had no luck. If anyone can open the .pcb file i would...
View ArticleForum Post: RE: Import a reference design into OrCAD
You can try to download one of the free viewers here and see if it can open it. I have this Pads Layout Viewer and it can open up Mentor Graphics Pads designs that are .pcb. Worth a try....
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