Forum Post: RE: explicit wire decalration by virtuoso verilog netlister
Hi Andrew, I have the same need. The problem is that I perform a post elaboration of the netlist changing all the input, output, inout ports and declared wires type to a user defined nettype(this is...
View ArticleForum Post: RE: Disconnecting the IO Port Net
did you try the -port option of attachTerm? see the docs for detachTerm, regarding detaching a port and why it's not allowed.
View ArticleForum Post: RE: CCL map file for RC extraction in Cadence. How to convert my...
see if this helps: support.cadence.com/.../L2dBISEvZ0FBIS9nQSEh
View ArticleForum Post: RE: Driver/Receivers Delay in Time Analysis
if you use report_timing -net, the timing report will separate the cell and net delays into separate lines. you can also turn on the fanout column to see that information. check the documentation for...
View ArticleForum Post: RE: High Fanout nets synthesis encounter
you need to figure out why that net doesn't seem to have a driver. sounds like something might be wrong with the netlist. as for VDD/VSS, BTS should not be trying to buffer those if you didn't list...
View ArticleForum Post: RE: Connectivity Violation
hard to tell without seeing the design. did you visually check to see if the routing was there in the first case?
View ArticleForum Post: RE: cdf Parameter access through OA scripting
Thank you for the prompt response.
View ArticleForum Post: RE: ecounter read_activity_file with SAF issue
i don't think SAF and SAIF are the same, but i'm not familiar with either format.
View ArticleForum Post: RE: Unable to add VDD VSS pins to the verilog netlist generated...
did you declare your pwr/gnd nets in the .globals file? seems like encounter doesn't know that you have pwr/gnd nets or what they are called.
View ArticleForum Post: RE: what are power file and power net pad file?
i'm not sure what you are looking for in terms of what is dumped out. when looking at EM violations, you should look for the "rj" section in the file called "results". Any data points above 1.0...
View ArticleForum Post: RE: There is no .lib created with saveModel in Encounter, please...
sounds like this should have worked. were any errors or warnings issued? you may need to file a service request.
View ArticleForum Post: RE: Problem with Verilog-defined power/ground nets and pins...
you might want to post this to CustomIC and maybe a verilog expert there can help. It seems like the direction is getting mangled from INOUT to OUTPUT somewhere - but I'm not a verilog expert, so...
View ArticleForum Post: RE: Suppressing HDL Parser Warning and port mismatch warnings
Hi Andrey, You can find the list of variables and their default settings (per tool) by looking in your installation hierarchy, for example for the schematic tool the 'central' .cdsenv is here:...
View ArticleForum Post: RE: Black Blox Creation
You do not want the black-box function, this i for excluding parts of the design completely and you can't simulate if you do that. You need the MSIE flow; you'll need to snapshots, one with your DUT_1...
View ArticleForum Post: RE: skill mode download?
Historically I've asked people to send me a private message with their email details (actually you have to send a friend request because my profile is such that I only allow private messages from...
View ArticleForum Post: RE: Invalid CDF choice
The properties are gone, I double checked. As a first solution I'm gonna rename my CDF parameters. It's a bit of a strange error since it only happens in combination with synchronous copy clones, and...
View ArticleForum Post: [AHB eVC]Unexpected 1ps delay on BFM
Hi, Another question on AHB eVC. For some reason, when the master agent drives the AHB signals (to be specific, HSIZE and HADDR), sometimes there will be a 1ps delay(clock period is 3.75ns). It may or...
View ArticleForum Post: RE: Quickly schematic-viewing a gates file
The timescale is only needed if your design has a mixture of modules with and without timescales. If you're not interested in simulating and only want to browse the schematic, just invent a timescale:...
View ArticleForum Post: RE: Quickly schematic-viewing a gates file
I know, I was only saying that there are too many steps involved in just 'viewing' a gates file Thanks Stephen
View ArticleForum Post: RE: skill mode download?
Here is a copy : github.com/.../skillmode4.4.tar.gz
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